2015-2016 Microchip Technology Inc. DS20005386B-page 23
PAC1710/20
6.0 REGISTERS IN HEXADECIMAL ORDER
The registers shown in Tab le 6- 1 are accessible through the SMBus. In the
individual register tables that follow, an entry of ‘
—’ indicates that the bit is not
used and will always read ‘0’.
TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER
Register
Address
Register
Name
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Default
Value
00h Configuration
— CDEN MSKAL C2IDS C2VDS TOUT C1IDS C1VDS 00h
01h Conversion Rate
— — — — — — CONV1 CONV0 03h
02h One-Shot OS7 OS6 OS5 OS4 OS3 OS2 OS1 OS0 00h
03h Channel Mask Register
— — — — C2VS C2VSR C1VS C1VSR 00h
04h High-Limit Status CVDN
— — — C2VSH C2VRH C1VSH C1VRH 00h
05h Low-Limit Status
— — — — C2VSL C2VRL C1VSL C1VRL 00h
0Ah V
SOURCE
Sampling
Configuration
C2RS1 C2RS0 C2RA1 C2RA0 C1RS1 C1RS0 C1RA1 C1RA0 88h
0Bh CH1 V
SENSE
Sampling
Configuration
— C1SS2 C1SS1 C1SS0 C1SA1 C1SA0 C1SR1 C1SR0 53h
0Ch CH2 V
SENSE
Sampling
Configuration
— C2SS2 C2SS1 C2SS0 C2SA1 C2SA0 C2SR1 C2SR0 53h
0Dh CH1 Sense Voltage
High Byte
C1SR11 C1SR10 C1SR9 C1SR8 C1SR7 C1SR6 C1SR5 C1SR4 00h
0Eh CH1 Sense Voltage
Low Byte
C1SR3 C1SR2 C1SR1 C1SR0
— — — — 00h
0Fh CH2 Sense Voltage
High Byte
C2SR11 C2SR10 C2SR9 C2SR8 C2SR7 C2SR6 C2SR5 C2SR4 00h
10h CH2 Sense Voltage
Low Byte
C2SR3 C2SR2 C2SR1 C2SR0 — — — — 00h
11 CH1 V
SOURCE
Voltage
High Byte
C1VR10 C1VR9 C1VR8 C1VR7 C1VR6 C1VR5 C1VR4 C1VR3 00h
12 CH1 V
SOURCE
Voltage
Low Byte
C1VR2 C1VR1 C1VR0 — — — — — 00h
13h CH2 V
SOURCE
Voltage
High Byte
C2VR10 C1VR9 C2VR8 C2VR7 C2VR6 C2VR5 C2VR4 C2VR3 00h
14h CH2 V
SOURCE
Voltage
Low Byte
C2VR2 C2VR1 C2VR0 — — — — — 00h
