LPC2919FBD144/01/,

1. Introduction

1.1 About this document

This document lists detailed information about the LPC2917/19 device. It focuses on

factual information like pinning, characteristics etc. Short descriptions are used to outline

the concept of the features and functions. More details and background on developing

applications for this device are given in the LPC2917/19 User manual (see Ref. 1). No

explicit references are made to the User manual.

1.2 Intended audience

This document is written for engineers evaluating and/or developing systems, hard- and/or

• An AMBA Advanced High-performance Bus (AHB) for interfacing to the on-chip

memory controllers

• Two DTL buses (a universal NXP interface) for interfacing to the interrupt controller

and the Power, Clock and Reset Control cluster (also called subsystem)

• Three ARM Peripheral Buses (APB - a compatible superset of ARM's AMBA

advanced peripheral bus) for connection to on-chip peripherals clustered in

subsystems.

• One ARM Peripheral Bus for event router and system control.

The LPC2917/19 configures the ARM968E-S processor in little-endian byte order. All

peripherals run at their own clock frequency to optimize the total system power

ARM9 microcontroller with CAN and LIN

Rev. 01 — 31 July 2008 Product data sheet

LPC2917_19_1 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 01 — 31 July 2008 2 of 67

NXP Semiconductors

LPC2917/19

2.2 ARM968E-S processor

The ARM968E-S is a general purpose 32-bit RISC processor, which offers high

performance and very low power consumption. The ARM architecture is based on RISC

interfaces

• Write buffers for the AHB and TCM buses

• Enhanced 16 × 32 multiplier capable of single-cycle MAC operations and 16-bit fixed-

point DSP instructions to accelerate signal-processing algorithms and applications.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. The ARM968E-S is based on the ARMv5TE five-stage pipeline

architecture. Typically, in a three-stage pipeline architecture, while one instruction is being

executed its successor is being decoded and a third instruction is being fetched from

memory. In the five-stage pipeline additional stages are added for memory access and

write-back cycles.

• 16-bit Thumb set

The Thumb set's 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM's performance advantage over a

traditional 16-bit controller using 16-bit registers. This is possible because Thumb code

operates on the same 32-bit register set as ARM code.

Thumb code can provide up to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM controller connected to a 16-bit memory system.

2.3 On-chip flash memory system

The LPC2917/19 includes a 512 kB or 768 kB flash memory system. This memory can be

used for both code and data storage. Programming of the flash memory can be

LPC2917_19_1 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 01 — 31 July 2008 3 of 67

NXP Semiconductors

LPC2917/19

2.4 On-chip static RAM

In addition to the two 16 kB TCMs the LPC2917/19 includes two static RAM memories:

one of 32 kB and one of 16 kB. Both may be used for code and/or data storage.

n On-chip memory:

u Two Tightly Coupled Memories (TCM), 16 kB Instruction TCM (ITCM), 16 kB Data

TCM (DTCM).

u Two separate internal SRAM instances; 32 kB and 16 kB.

u Up to 768 kB flash program memory.

n Two-channel CAN controller supporting Full-CAN and extensive message filtering.

n Two LIN master controllers with full hardware support for LIN communication.

n Two 550 UARTs with 16-byte TX and RX FIFO depths.

n Three full-duplex queued SPIs with four slave-select lines; 16 bits wide; 8 locations

n Four 32-bit timers each containing four capture-and-compare registers linked to I/Os.

n Vectored Interrupt Controller (VIC) with 16 priority levels.

n Up to 24 level-sensitive external interrupt pins, including CAN and LIN wake-up

n External Static Memory Controller (SMC) with eight memory banks; up to 32-bit data

n Processor wake-up from power-down via external interrupt pins; CAN or LIN activity.

n Flexible Reset Generation Unit (RGU) able to control resets of individual modules.

n Flexible Clock Generation Unit (CGU) able to control clock frequency of individual

u On-chip very low-power ring oscillator; fixed frequency of 0.4 MHz; always on to

n Highly configurable system Power Management Unit (PMU):

u Clock control of individual modules.