LPC2917_19_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 31 July 2008 47 of 67
NXP Semiconductors
LPC2917/19
ARM9 microcontroller with CAN and LIN
The key features are:
• Individual clock control for all LPC2917/19 sub-modules
• Activates sleeping clocks when a wake-up event is detected
• Clocks can be individually disabled by software
• Supports AHB master-disable protocol when AUTO mode is set
• Disables wake-up of enabled clocks when Power-down mode is set
• Activates wake-up of enabled clocks when a wake-up event is received
• Status register is available to indicate if an input base clock can be safely switched off
(i.e., all branch clocks are disabled)
8.8.6.2 Description
The PMU controls all internal clocks of the device for power-mode management. With
some exceptions, each branch clock can be switched on or off individually under control of
software register bits located in its individual configuration register. Some branch clocks
controlling vital parts of the device operate in a fixed mode. Table 27 shows which mode-
control bits are supported by each branch clock.
By programming the configuration register the user can control which clocks are switched
on or off, and which clocks are switched off when entering Power-down mode.
Note that the standby-wait-for-interrupt instructions of the ARM968E-S processor (putting
the ARM CPU into a low-power state) are not supported. Instead putting the ARM CPU
into power-down should be controlled by disabling the branch clock for the CPU.
Remark: For any disabled branch clocks to be re-activated their corresponding base
clocks must be running (controlled by the CGU).
Table 27 shows the relation between branch and base clocks, see also Section 7.2.1.
Every branch clock is related to one particular base clock: it is not possible to switch the
source of a branch clock in the PMU.
Table 27. Branch clock overview
Legend:
‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored
‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored
‘+’ Indicates that the related register bit is readable and writable
Branch clock name Base clock Implemented switch on/off
mechanism
WAKE-UP AUTO RUN
CLK_SAFE BASE_SAFE_CLK 0 0 1
CLK_SYS_CPU BASE_SYS_CLK + + 1
CLK_SYS BASE_SYS_CLK + + 1
CLK_SYS_PCR BASE_SYS_CLK + + 1
CLK_SYS_FMC BASE_SYS_CLK + + +
CLK_SYS_RAM0 BASE_SYS_CLK + + +
CLK_SYS_RAM1 BASE_SYS_CLK + + +
CLK_SYS_SMC BASE_SYS_CLK + + +
CLK_SYS_GESS BASE_SYS_CLK + + +
