LPC2919FBD144/01/, Datasheet LPC2919FBD144/01/,, LPC2917FBD144/01/,, OM11014 | P25-P27

Product data sheet Rev. 01 — 31 July 2008 25 of 67

NXP Semiconductors

LPC2917/19

ARM9 microcontroller with CAN and LIN

timers and their associated pins. The timer pins are combined with other functions on the

port pins of the LPC2917/19, see Section 8.3.3. Table Table 14 shows the timer pins (x

runs from 0 to 3).

8.4.3.4 Timer clock description

The timer modules are clocked by two different clocks; CLK_SYS_PESS and CLK_TMRx

(x = 0-3), see Section 7.2.2. Note that each timer has its own CLK_TMRx branch clock for

power management. The frequency of all these clocks is identical as they are derived from

the same base clock BASE_CLK_TMR. The register interface towards the system bus is

clocked by CLK_SYS_PESS. The timer and prescale counters are clocked by

CLK_TMRx.

8.4.4 UARTs

8.4.4.1 Overview

The LPC2917/19 contains two identical UARTs located at different peripheral base

addresses. The key features are:

• 16-byte receive and transmit FIFOs

• Register locations conform to 550 industry standard

• Receiver FIFO trigger points at 1 byte, 4 bytes, 8 bytes and 14 bytes

• Built-in baud rate generator

8.4.4.2 Description

The UART is commonly used to implement a serial interface such as RS232. The

LPC2917/19 contains two industry-standard 550 UARTs with 16-byte transmit and receive

FIFOs, but they can also be put into 450 mode without FIFOs.

8.4.4.3 UART pin description

The two UARTs in the LPC2917/19 have the following pins. The UART pins are combined

with other functions on the port pins of the LPC2917/19. Table 15 shows the UART pins (x

runs from 0 to 1).

Table 14. Timer pins

Symbol Direction Description

TIMERx CAP[0] IN TIMER x capture input 0

TIMERx CAP[1] IN TIMER x capture input 1

TIMERx CAP[2] IN TIMER x capture input 2

TIMERx CAP[3] IN TIMER x capture input 3

TIMERx MAT[0] OUT TIMER x match output 0

TIMERx MAT[1] OUT TIMER x match output 1

TIMERx MAT[2] OUT TIMER x match output 2

TIMERx MAT[3] OUT TIMER x match output 3

Table 15. UART pins

Symbol Direction Description

UARTx TXD OUT UART channel x transmit data output

UARTx RXD IN UART channel x receive data input

Product data sheet Rev. 01 — 31 July 2008 26 of 67

NXP Semiconductors

LPC2917/19

ARM9 microcontroller with CAN and LIN

8.4.4.4 UART clock description

The UART modules are clocked by two different clocks; CLK_SYS_PESS and

CLK_UARTx (x = 0-1), see Section 7.2.2. Note that each UART has its own CLK_UARTx

branch clock for power management. The frequency of all CLK_UARTx clocks is identical

since they are derived from the same base clock BASE_CLK_UART. The register

interface towards the system bus is clocked by CLK_SYS_PESS. The baud generator is

clocked by the CLK_UARTx.

8.4.5 Serial peripheral interface

8.4.5.1 Overview

The LPC2917/19 contains three SPI modules to allow synchronous serial communication

with slave or master peripherals.

The key features are:

• Master or slave operation

• Supports up to four slaves in sequential multi-slave operation

• Supports timer-triggered operation

• Programmable clock bit rate and prescale based on SPI source clock

(BASE_SPI_CLK), independent of system clock

• Separate transmit and receive FIFO memory buffers; 16 bits wide, 32 locations deep

• Programmable choice of interface operation: Motorola SPI or Texas Instruments

Synchronous Serial Interfaces

• Programmable data-frame size from 4 to 16 bits

• Independent masking of transmit FIFO, receive FIFO and receive overrun interrupts

• Serial clock-rate master mode: fserial_clk ≤ f

CLK(SPI)*

• Serial clock-rate slave mode: fserial_clk = f

CLK(SPI)*

• Internal loopback test mode

8.4.5.2 Functional description

The SPI module is a master or slave interface for synchronous serial communication with

peripheral devices that have either Motorola SPI or Texas Instruments Synchronous Serial

Interfaces.

The SPI module performs serial-to-parallel conversion on data received from a peripheral

device. The transmit and receive paths are buffered with FIFO memories (16 bits wide ×

32 words deep). Serial data is transmitted on SPI_TXD and received on SPI_RXD.

The SPI module includes a programmable bit-rate clock divider and prescaler to generate

the SPI serial clock from the input clock CLK_SPIx.

The SPI module’s operating mode, frame format, and word size are programmed through

the SLVn_SETTINGS registers.

A single combined interrupt request SPI_INTREQ output is asserted if any of the

interrupts are asserted and unmasked.

Product data sheet Rev. 01 — 31 July 2008 27 of 67

NXP Semiconductors

LPC2917/19

ARM9 microcontroller with CAN and LIN

Depending on the operating mode selected, the SPI_CS_OUT outputs operate as an

active-HIGH frame synchronization output for Texas Instruments synchronous serial

frame format or an active-LOW chip select for SPI.

Each data frame is between four and 16 bits long, depending on the size of words

programmed, and is transmitted starting with the MSB.

There are two basic frame types that can be selected:

• Texas Instruments synchronous serial

• Motorola Serial Peripheral Interface

8.4.5.3 Modes of operation

The SPI module can operate in:

• Master mode:

– Normal transmission mode

– Sequential slave mode

• Slave mode

8.4.5.4 SPI pin description

The three SPI modules in the LPC2917/19 have the pins listed below. The pins are

combined with other functions on the port pins of the LPC2917/19, see Section 8.3.3.

Table 16 shows the SPI pins (x runs from 0 to 2; y runs from 0 to 3).

[1] Direction of SPIx SCS and SPIx SCK pins depends on master or slave mode. These pins are output in

master mode, input in slave mode.

[2] In slave mode there is only one chip select input pin, SPIx SCS0. The other chip selects have no function in

slave mode.

8.4.5.5 SPI clock description

The SPI modules are clocked by two different clocks; CLK_SYS_PESS and CLK_SPIx

(x = 0-2), see Section 7.2.2. Note that each SPI has its own CLK_SPIx branch clock for

power management. The frequency of all clocks CLK_SPIx is identical as they are derived

from the same base clock BASE_CLK_SPI. The register interface towards the system bus

is clocked by CLK_SYS_PESS. The serial-clock rate divisor is clocked by CLK_SPIx.

The SPI clock frequency can be controlled by the CGU. In master mode the SPI clock

frequency (CLK_SPIx) must be set to at least twice the SPI serial clock rate on the

interface. In slave mode CLK_SPIx must be set to four times the SPI serial clock rate on

the interface.

Table 16. SPI pins

Symbol Direction Description

SPIx SCSy IN/OUT SPIx chip select

[1][2]

SPIx SCK IN/OUT SPIx clock

[1]

SPIx SDI IN SPIx data input

SPIx SDO OUT SPIx data output

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