LPC2919FBD144/01/, Datasheet LPC2919FBD144/01/,, LPC2917FBD144/01/,, OM11014 | P28-P30

Product data sheet Rev. 01 — 31 July 2008 28 of 67

NXP Semiconductors

LPC2917/19

ARM9 microcontroller with CAN and LIN

8.4.6 General-purpose I/O

8.4.6.1 Overview

The LPC2917/19 contains four general-purpose I/O ports located at different peripheral

base addresses. In the 144-pin package all four ports are available. All I/O pins are

bidirectional, and the direction can be programmed individually. The I/O pad behavior

depends on the conﬁguration programmed in the port function-select registers.

The key features are:

• General-purpose parallel inputs and outputs

• Direction control of individual bits

• Synchronized input sampling for stable input-data values

• All I/O defaults to input at reset to avoid any possible bus conﬂicts

8.4.6.2 Description

The general-purpose I/O provides individual control over each bidirectional port pin. There

are two registers to control I/O direction and output level. The inputs are synchronized to

achieve stable read-levels.

To generate an open-drain output, set the bit in the output register to the desired value.

Use the direction register to control the signal. When set to output, the output driver

actively drives the value on the output: when set to input the signal ﬂoats and can be

pulled up internally or externally.

8.4.6.3 GPIO pin description

The ﬁve GPIO ports in the LPC2917/19 have the pins listed below. The GPIO pins are

combined with other functions on the port pins of the LPC2917/19. Table 17 shows the

GPIO pins.

8.4.6.4 GPIO clock description

The GPIO modules are clocked by several clocks, all of which are derived from

BASE_SYS_CLK; CLK_SYS_PESS and CLK_SYS_GPIOx (x = 0-3), see Section 7.2.2.

Note that each GPIO has its own CLK__SYS_GPIOx branch clock for power

management. The frequency of all clocks CLK_SYS_GPIOx is identical to

CLK_SYS_PESS since they are derived from the same base clock BASE_SYS_CLK.

Table 17. GPIO pins

Symbol Direction Description

GPIO0 pin[31:0] IN/OUT GPIO port x pins 31 to 0

GPIO1 pin[31:0] IN/OUT GPIO port x pins 31 to 0

GPIO2 pin[27:0] IN/OUT GPIO port x pins 27 to 0

GPIO3 pin[15:0] IN/OUT GPIO port x pins 15 to 0

Product data sheet Rev. 01 — 31 July 2008 29 of 67

NXP Semiconductors

LPC2917/19

ARM9 microcontroller with CAN and LIN

8.5 CAN gateway

8.5.1 Overview

Controller Area Network (CAN) is the deﬁnition of a high-performance communication

protocol for serial data communication. The two CAN controllers in the LPC2917/19

provide a full implementation of the CAN protocol according to the

CAN speciﬁcation

version 2.0B

. The gateway concept is fully scalable with the number of CAN controllers,

and always operates together with a separate powerful and ﬂexible hardware acceptance

ﬁlter.

The key features are:

• Supports 11-bit as well as 29-bit identiﬁers

• Double receive buffer and triple transmit buffer

• Programmable error-warning limit and error counters with read/write access

• Arbitration-lost capture and error-code capture with detailed bit position

• Single-shot transmission (i.e., no re-transmission)

• Listen-only mode (no acknowledge; no active error ﬂags)

• Reception of ‘own’ messages (self-reception request)

• Full CAN mode for message reception

8.5.2 Global acceptance ﬁlter

The global acceptance ﬁlter provides look-up of received identiﬁers - called acceptance

ﬁltering in CAN terminology - for all the CAN controllers. It includes a CAN ID look-up table

memory, in which software maintains one to ﬁve sections of identiﬁers. The CAN ID

look-up table memory is 2 kB large (512 words, each of 32 bits). It can contain up to 1024

standard frame identiﬁers or 512 extended frame identiﬁers or a mixture of both types. It is

also possible to deﬁne identiﬁer groups for standard and extended message formats.

8.5.3 CAN pin description

The two CAN controllers in the LPC2917/19 have the pins listed below. The CAN pins are

combined with other functions on the port pins of the LPC2917/19. Table 18 shows the

CAN pins (x runs from 0 to 1).

8.6 LIN

8.6.1 Overview

The LPC2917/19 contain two LIN 2.0 master controllers. These can be used as dedicated

LIN 2.0 master controllers with additional support for sync break generation and with

hardware implementation of the LIN protocol according to spec 2.0.

The key features are:

Table 18. CAN pins

Symbol Direction Description

CANx TXDC OUT CAN channel x transmit data output

CANx RXDC IN CAN channel x receive data input

Product data sheet Rev. 01 — 31 July 2008 30 of 67

NXP Semiconductors

LPC2917/19

ARM9 microcontroller with CAN and LIN

• Complete LIN 2.0 message handling and transfer

• One interrupt per LIN message

• Slave response time-out detection

• Programmable sync-break length

• Automatic sync-ﬁeld and sync-break generation

• Programmable inter-byte space

• Hardware or software parity generation

• Automatic checksum generation

• Fault conﬁnement

• Fractional baud rate generator

8.6.2 LIN pin description

The two LIN 2.0 master controllers in the LPC2917/19 have the pins listed below. The LIN

pins are combined with other functions on the port pins of the LPC2917/19. Table 19

shows the LIN pins. For more information see Ref. 1 subsection 3.43, LIN master

controller.

8.7 Modulation and sampling control subsystem

8.7.1 Overview

The Modulation and Sampling Control Subsystem (MSCSS) in the LPC2917/19 includes

four Pulse-Width Modulators (PWMs), two 10-bit successive approximation

Analog-to-Digital Converters (ADCs) and two timers.

The key features of the MSCSS are:

• Two 10-bit, 400 ksample/s, 8-channel ADCs with 3.3 V inputs and various trigger-

start options

• Four 6-channel PWMs (Pulse-Width Modulators) with capture and trap functionality

• Two dedicated timers to schedule and synchronize the PWMs and ADCs

8.7.2 Description

The MSCSS contains Pulse-Width Modulators (PWMs), Analog-to-Digital Converters

(ADCs) and timers.

Figure 7 provides an overview of the MSCSS. An AHB-to-APB bus bridge takes care of

communication with the AHB system bus. Two internal timers are dedicated to this

subsystem. MSCSS timer 0 can be used to generate start pulses for the ADCs and the

ﬁrst PWM. The second timer (MSCSS timer 1) is used to generate ‘carrier’ signals for the

PWMs. These carrier patterns can be used, for example, in applications requiring current

Table 19. LIN controller pins

Symbol Direction Description

LIN0/1 TXDL OUT LIN channel 0/1 transmit data output

LIN0/1 RXDL IN LIN channel 0/1 receive data input

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P60 P61-P63 P64-P66 P67-P67

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