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LPC2919FBD144/01/,

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P67
LPC2917_19_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 31 July 2008 55 of 67
NXP Semiconductors
LPC2917/19
ARM9 microcontroller with CAN and LIN
[1] All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at T
amb
= 125 °C on wafer
level. Cased products are tested at T
amb
=25°C (final testing). Both pre-testing and final testing use correlated test conditions to cover
the specified temperature and power-supply voltage range.
[2] Leakage current is exponential to temperature; worst-case value is at 125 °C T
vj
. All clocks off. Analog modules and flash powered
down.
[3] For Port 0, pin 0 to pin 15 add maximum 1.5 pF for input capacitance to ADC. For Port 0, pin 16 to pin 31 add maximum 1.0 pF for input
capacitance to ADC.
[4] This value is the minimum drive capability. Maximum short-circuit output current is 33 mA (drive HIGH-level, shorted to ground) or
−38 mA. (drive LOW-level, shorted to V
DD(IO)
). The device will be damaged if multiple outputs are shorted.
[5] C
xtal
is crystal load capacitance and C
ext
are the two external load capacitors.
[6] The power-up reset has a time filter: V
DD(CORE)
must be above V
trip(high)
for 2 µs before reset is de-asserted; V
DD(CORE)
must be below
V
trip(low)
for 11 µs before internal reset is asserted.
[7] Not 5 V-tolerant when pull-up is on.
[8] For I/O Port 0, the maximum input voltage is defined by V
I(ADC)
.
[9] This parameter is not part of production testing or final testing, hence only a typical value is stated. Maximum and minimum values are
based on simulation results.
Power-up reset
V
trip(high)
high trip level voltage
[6]
1.1 1.4 1.6 V
V
trip(low)
low trip level voltage
[6]
1.0 1.3 1.5 V
V
trip(dif)
difference between high
and low trip level voltage
[6]
50 120 180 mV
Table 30. Static characteristics
…continued
V
DD(CORE)
=V
DD(OSC_PLL)
; V
DD(IO)
= 2.7 V to 3.6 V; V
DDA(ADC3V3)
= 3.0 V to 3.6 V; T
vj
= -40
°
C to +125
°
C; all voltages are
measured with respect to ground; positive currents flow into the IC; unless otherwise specified.
[1]
Symbol Parameter Conditions Min Typ Max Unit
LPC2917_19_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 31 July 2008 56 of 67
NXP Semiconductors
LPC2917/19
ARM9 microcontroller with CAN and LIN
12. Dynamic characteristics
Table 31. Dynamic characteristics
V
DD(CORE)
=V
DD(OSC_PLL)
;V
DD(IO)
= 2.7 V to 3.6 V; V
DDA(ADC3V3)
= 3.0 V to 3.6 V; T
vj
=
−
40
°
C; all voltages are measured with
respect to ground; positive currents flow into the IC; unless otherwise specified.
[1]
Symbol Parameter Conditions Min Typ Max Unit
I/O pins
t
THL
HIGH-to-LOW
transition time
C
L
= 30 pF 4 - 13.8 ns
t
TLH
LOW-to-HIGH
transition time
C
L
= 30 pF 4 - 13.8 ns
Internal clock
f
clk(sys)
system clock frequency
[2]
10 - 80 MHz
T
clk(sys)
system clock period
[2]
12.5 - 100 ns
Low-power ring oscillator
f
ref(RO)
RO reference
frequency
0.36 0.4 0.42 MHz
t
startup
start-up time at maximum frequency
[3]
- 6 100 µs
Oscillator
f
i(osc)
oscillator input
frequency
maximum frequency is
the clock input of an
external clock source
applied to the Xin pin
10 - 80 MHz
t
startup
start-up time at maximum frequency
[3]
[4]
- 500 - µs
PLL
f
i(PLL)
PLL input frequency 10 - 25 MHz
f
o(PLL)
PLL output frequency 10 - 160 MHz
CCO; direct mode 156 - 320 MHz
Analog-to-digital converter
f
i(ADC)
ADC input frequency
[5]
4 - 4.5 MHz
f
s(max)
maximum sampling
rate
f
i(ADC)
= 4.5 MHz;
f
s
=f
i(ADC)
/(n + 1) with
n = resolution
resolution 2 bit - - 1500 ksample/s
resolution 10 bit - - 400 ksample/s
t
conv
conversion time In number of ADC clock
cycles
3 - 11 cycles
In number of bits 2 - 10 bits
Flash memory
t
init
initialization time - - 150 µs
t
wr(pg)
page write time 0.95 1 1.05 ms
t
er(sect)
sector erase time 95 100 105 ms
t
fl(BIST)
flash word BIST time - 38 70 ns
t
a(clk)
clock access time - - 63.4 ns
t
a(A)
address access time - - 60.3 ns
LPC2917_19_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 31 July 2008 57 of 67
NXP Semiconductors
LPC2917/19
ARM9 microcontroller with CAN and LIN
[1] All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at T
amb
= 125 °C ambient
temperature on wafer level. Cased products are tested at T
amb
=25°C (final testing). Both pre-testing and final testing use correlated
test conditions to cover the specified temperature and power supply voltage range.
[2] See Table 23.
[3] This parameter is not part of production testing or final testing, hence only a typical value is stated.
[4] Oscillator start-up time depends on the quality of the crystal. For most crystals it takes about 1000 clock pulses until the clock is fully
stable.
[5] Duty cycle clock should be as close as possible to 50 %.
External static memory controller
t
a(R)int
internal read access
time
- - 20.5 ns
t
a(W)int
internal write access
time
- - 24.9 ns
UART
f
UART
UART frequency
1
⁄
65024
f
clk(uart)
-
1
⁄
2
f
clk(uart)
MHz
SPI
f
SPI
SPI operating
frequency
master operation
1
⁄
65024
f
clk(spi)
-
1
⁄
2
f
clk(spi)
MHz
slave operation
1
⁄
65024
f
clk(spi)
-
1
⁄
4
f
clk(spi)
MHz
Jitter specification
t
jit(cc)(p-p)
cycle to cycle jitter
(peak-to-peak value)
on CAN TXDC pin
[3]
- 0.4 1 ns
Table 31. Dynamic characteristics
…continued
V
DD(CORE)
=V
DD(OSC_PLL)
;V
DD(IO)
= 2.7 V to 3.6 V; V
DDA(ADC3V3)
= 3.0 V to 3.6 V; T
vj
=
−
40
°
C; all voltages are measured with
respect to ground; positive currents flow into the IC; unless otherwise specified.
[1]
Symbol Parameter Conditions Min Typ Max Unit
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P67

LPC2919FBD144/01/,

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Buy LPC2919FBD144/01/,
Manufacturer:
NXP Semiconductors
Description:
ARM Microcontrollers - MCU ARM968 768K FL/48K
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