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LPC2919FBD144/01/,

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P67
LPC2917_19_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 31 July 2008 16 of 67
NXP Semiconductors
LPC2917/19
ARM9 microcontroller with CAN and LIN
8.1.3 Flash memory controller pin description
The flash memory controller has no external pins. However, the flash can be programmed
via the JTAG pins, see Section 7.1.3.
8.1.4 Flash memory controller clock description
The flash memory controller is clocked by CLK_SYS_FMC, see Section 7.2.2.
8.1.5 Flash layout
The ARM processor can program the flash for ISP (In-System Programming) and IAP (In-
Application Programming). Note that the flash always has to be programmed by ‘flash
words’ of 128 bits (four 32-bit AHB bus words, hence 16 bytes).
The flash memory is organized into eight ‘small’ sectors of 8 kB each and up to 11 ‘large’
sectors of 64 kB each. The number of large sectors depends on the device type. A sector
must be erased before data can be written to it. The flash memory also has sector-wise
protection. Writing occurs per page which consists of 4096 bits (32 flash words). A small
sector contains 16 pages; a large sector contains 128 pages.
Table 9 gives an overview of the flash sector base addresses.
Table 8. Flash read modes
Synchronous timing
No buffer line for single (non-linear) reads; one flash word read per word read
Single buffer line default mode of operation; most recently read flash word is kept until
another flash word is required
Asynchronous timing
No buffer line one flash word read per word read
Single buffer line most recently read flash word is kept until another flash word is
required
Dual buffer line, single
speculative
on a buffer miss a flash read is done, followed by at most one
speculative read; optimized for execution of code with small loops
(less than eight words) from flash
Dual buffer line, always
speculative
most recently used flash word is copied into second buffer line; next
flash word read is started; highest performance for linear reads
Table 9. Flash sector overview
Sector number Sector size (kB) Sector base address
0 8 0000 0000h
1 8 0000 2000h
2 8 0000 4000h
3 8 0000 6000h
4 8 0000 8000h
5 8 0000 A000h
6 8 0000 C000h
7 8 0000 E000h
8 64 0001 0000h
9 64 0002 0000h
10 64 0003 0000h
LPC2917_19_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 31 July 2008 17 of 67
NXP Semiconductors
LPC2917/19
ARM9 microcontroller with CAN and LIN
[1] Availability of sector 15 to sector 18 depends on device type, see Section 4 “Ordering information”.
The index sector is a special sector in which the JTAG access protection and sector
security are located. The address space becomes visible by setting the FS_ISS bit and
overlaps the regular flash sector’s address space.
Note that the index sector cannot be erased, and that access to it has to be performed via
code outside the flash.
8.1.6 Flash bridge wait-states
To eliminate the delay associated with synchronizing flash read data, a predefined number
of wait-states must be programmed. These depend on flash memory response time and
system clock period. The minimum wait-states value can be calculated with the following
formulas:
Synchronous reading:
(1)
Asynchronous reading:
(2)
Remark: If the programmed number of wait-states is more than three, flash data reading
cannot be performed at full speed (i.e., with zero wait-states at the AHB bus) if speculative
reading is active.
8.2 External static memory controller
8.2.1 Overview
The LPC2917/19 contains an external Static Memory Controller (SMC) which provides an
interface for external (off-chip) memory devices.
Key features are:
• Supports static memory-mapped devices including RAM, ROM, flash, burst ROM and
external I/O devices
11 64 0004 0000h
12 64 0005 0000h
13 64 0006 0000h
14 64 0007 0000h
15
[1]
64 0008 0000h
16
[1]
64 0009 0000h
17
[1]
64 000A 0000h
18
[1]
64 000B 0000h
Table 9. Flash sector overview
…continued
Sector number Sector size (kB) Sector base address
WST
t
acc clk()
t
t
tclk sys()
------------------
> 1–
WST
t
acc addr()
t
tclk sys()
----------------------
> 1–
LPC2917_19_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 31 July 2008 18 of 67
NXP Semiconductors
LPC2917/19
ARM9 microcontroller with CAN and LIN
• Asynchronous page-mode read operation in non-clocked memory subsystems
• Asynchronous burst-mode read access to burst-mode ROM devices
• Independent configuration for up to eight banks, each up to 16 MB
• Programmable bus-turnaround (idle) cycles (one to 16)
• Programmable read and write wait states (up to 32), for static RAM devices
• Programmable initial and subsequent burst-read wait state for burst-ROM devices
• Programmable write protection
• Programmable burst-mode operation
• Programmable external data width: 8 bits, 16 bits or 32 bits
• Programmable read-byte lane enable control
8.2.2 Description
The SMC simultaneously supports up to eight independently configurable memory banks.
Each memory bank can be 8 bits, 16 bits or 32 bits wide and is capable of supporting
SRAM, ROM, burst-ROM memory or external I/O devices.
A separate chip select output is available for each bank. The chip select lines are
configurable to be active HIGH or LOW. Memory-bank selection is controlled by memory
addressing. Table 10 shows how the 32-bit system address is mapped to the external bus
memory base addresses, chip selects and bank internal addresses.
Table 10. External memory-bank address bit description
32-bit
system
address bit
field
Symbol Description
31 to 29 BA[2:0] external static-memory base address (three most significant bits);
the base address can be found in the memory map; see
Ref. 1. This
field contains ‘010’ when addressing an external memory bank.
28 to 26 CS[2:0] chip select address space for eight memory banks; see
[1]
25 and 24 - always ‘00’; other values are ‘mirrors’ of the 16 MB bank address
23 to 0 A[23:0] 16 MB memory banks address space
Table 11. External static-memory controller banks
CS[2:0] Bank
000 bank 0
001 bank 1
010 bank 2
011 bank 3
100 bank 4
101 bank 5
110 bank 6
111 bank 7
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P67

LPC2919FBD144/01/,

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NXP Semiconductors
Description:
ARM Microcontrollers - MCU ARM968 768K FL/48K
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