SC16C654DBIB64,151 Datasheet SC16C654BIA68,518, SC16C654DBIB64,151, SC16C654BIBM,151 | P10-P12

Product data sheet Rev. 02 — 20 June 2005 10 of 58

Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

5.2 Pin description

Table 2: Pin description

Symbol Pin Type Description

PLCC68 LQFP64 HVQFN48 LFBGA6

16/

68 31 - 14 - I 16/68 Interface type select (input with internal pull-up).

This input provides the 16 (Intel) or 68 (Motorola) bus

interface type select. The functions of

IOR, IOW,

INTA to INTD, and

CSA to CSD are re-assigned with the

logical state of this pin. When this pin is a logic 1, the

16 mode interface (16C654) is selected. When this pin is a

logic 0, the 68 mode interface (68C654) is selected. When

this pin is a logic 0,

IOW is re-assigned to R/W, RESET is

re-assigned to

RESET, IOR is not used, and INTA to INTD

are connected in a wire-OR conﬁguration. The wire-OR

outputs are connected internally to the open-drain IRQ

signal output. This pin is not available on 64-pin packages

which operate in the 16 mode only.

A0 34 24 17 K5 I Address 0 select bit. Internal registers address selection in

16 and 68 modes.

A1 33 23 16 J5 I Address 1 select bit. Internal registers address selection in

16 and 68 modes.

A2 32 22 15 K4 I Address 2 select bit. Internal registers address selection in

16 and 68 modes.

A3 20 - 9 - I Address 3, Address 4 select bits. When the 68 mode is

selected, these pins are used to address or select individual

UARTs (providing

CS is a logic 0). In the 16 mode, these

pins are re-assigned as chip selects, see

CSB and CSC.

These pins are not available on 64-pin packages which

operate in the 16 mode only.

A4 50 - 31 -

CDA9 64 - A1 ICarrier Detect (active LOW). These inputs are associated

with individual UART channels A through D. A logic 0 on this

pin indicates that a carrier has been detected by the modem

for that channel.

CDB 27 18 - K2

CDC 43 31 24 J9

CDD 61 49 - A10

CLKSEL 30 - - - I Clock Select. The 1× or 4× pre-scalable clock is selected by

this pin. The 1× clock is selected when CLKSEL is a logic 1

(connected to V

) or the 4× is selected when CLKSEL is a

logic 0 (connected to GND). MCR[7] can override the state

of this pin following reset or initialization (see MCR[7]). This

pin is not available on 64-pin packages which provide

MCR[7] selection only.

CS 16 - 5 - I Chip Select (active LOW). In the 68 mode, this pin

functions as a multiple channel chip enable. In this case, all

four UARTs (A to D) are enabled when the

CS pin is a

logic 0. An individual UART channel is selected by the data

contents of address bits A[3:4]. when the 16 mode is

selected (68-pin devices), this pin functions as

CSA (see

deﬁnition under

CSA, CSB). This pin is not available on

64-pin packages which operate in the 16 mode only.

Product data sheet Rev. 02 — 20 June 2005 11 of 58

Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

CSA 16 7 5 E1 I Chip Select A, B, C, D (active LOW). This function is

associated with the 16 mode only, and for individual

channels ‘A’ through ‘D’. When in 16 mode, these pins

enable data transfers between the user CPU and the

SC16C654B/654DB for the channel(s) addressed. Individual

UART sections (A, B, C, D) are addressed by providing a

logic 0 on the respective

CSA to CSD pin. When the

68 mode is selected, the functions of these pins are

re-assigned. 68 mode functions are described under their

respective name/pin headings.

CSB 20 11 9 G1

CSC 50 38 31 G9

CSD 54 42 35 E9

CTSA 11 2 1 C1 I Clear to Send (active LOW). These inputs are associated

with individual UART channels A through D. A logic 0 on the

CTS pin indicates the modem or data set is ready to accept

transmit data from the SC16C654B/654DB. Status can be

tested by reading MSR[4]. This pin only affects the transmit

or receive operations when Auto CTS function is enabled via

the Enhanced Feature Register EFR[7] for hardware ﬂow

control operation.

CTSB 25 16 12 J2

CTSC 45 33 26 K10

CTSD 59 47 - B10

D0 to D2,

D3 to D7

66 to 68

, 1to5

53 to 55,

56 to 60

39 to 41,

42 to 46

B7, A7,

B6, A6,

B5, A5,

B4, A4

I/O Data bus (bi-directional). These pins are the 8-bit, 3-state

data bus for transferring information to or from the controlling

CPU. D0 is the least signiﬁcant bit and the ﬁrst data bit in a

transmit or receive serial data stream.

DSRA 10 1 - B1 I Data Set Ready (active LOW). These inputs are associated

with individual UART channels, A through D. A logic 0 on this

pin indicates the modem or data set is powered-on and is

ready for data exchange with the UART. This pin has no

effect on the UART’s transmit or receive operation.

DSRB 26 17 - K1

DSRC 44 32 25 K9

DSRD 60 48 - B9

DTRA 12 3 - D1 O Data Terminal Ready (active LOW). These outputs are

associated with individual UART channels, A through D. A

logic 0 on this pin indicates that the SC16C654B/654DB is

powered-on and ready. This pin can be controlled via the

modem control register. Writing a logic 1 to MCR[0] will set

the

DTR output to logic 0, enabling the modem. This pin will

be a logic 1 after writing a logic 0 to MCR[0], or after a reset.

This pin has no effect on the UART’s transmit or receive

operation.

DTRB 24 15 - J1

DTRC 46 34 27 J10

DTRD 58 46 - C9

GND 6, 23,

40, 57

14, 28,

45, 61

21, 37, 47 B3, K7,

H1, D9

I Signal and power ground.

INTA 15 6 4 D2 O Interrupt A, B, C, D (active HIGH). This function is

associated with the 16 mode only. These pins provide

individual channel interrupts INTA to INTD. INTA to INTD are

enabled when MCR[3] is set to a logic 1, interrupts are

enabled in the interrupt enable register (IER), and when an

interrupt condition exists. Interrupt conditions include:

receiver errors, available receiver buffer data, transmit buffer

empty, or when a modem status ﬂag is detected. When the

68 mode is selected, the functions of these pins are

re-assigned. 68 mode functions are described under their

respective name/pin headings.

INTB 21 12 10 G2

INTC 49 37 30 G10

INTD 55 43 36 D10

Table 2: Pin description

…continued

Symbol Pin Type Description

PLCC68 LQFP64 HVQFN48 LFBGA6

Product data sheet Rev. 02 — 20 June 2005 12 of 58

Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

INTSEL 65 - - - I Interrupt Select (active HIGH, with internal pull-down).

This function is associated with the 16 mode only. When the

16 mode is selected, this pin can be used in conjunction with

MCR[3] to enable or disable the 3-state interrupts,

INTA to INTD, or override MCR[3] and force continuous

interrupts. Interrupt outputs are enabled continuously by

making this pin a logic 1. Making this pin a logic 0 allows

MCR[3] to control the 3-state interrupt output. In this mode,

MCR[3] is set to a logic 1 to enable the 3-state outputs. This

pin is disabled in the 68 mode. Due to pin limitations on the

64-pin packages, this pin is not available. To cover this

limitation, the SC16C654DBIB64 version operates in the

continuous interrupt enable mode by bonding this pin to V

internally. The SC16C654BIB64 operates with MCR[3]

control by bonding this pin to GND.

IOR 52 40 33 F9 I Input/Output Read strobe (active LOW). This function is

associated with the 16 mode only. A logic 0 transition on this

pin will load the contents of an internal register deﬁned by

address bits A[0:2] onto the SC16C654B/654DB data bus

(D[0:7]) for access by external CPU. This pin is disabled in

the 68 mode.

IOW18 9 7 F1 IInput/Output Write strobe (active LOW). This function is

associated with the 16 mode only. A logic 0 transition on this

pin will transfer the contents of the data bus (D[0:7]) from the

external CPU to an internal register that is deﬁned by

address bits A[0:2]. When the 68 mode is selected

(PLCC68), this pin functions as R/

W (see deﬁnition under

W).

IRQ 15 - 4 - O Interrupt Request or Interrupt ‘A’. This function is

associated with the 68 mode only. In the 68 mode, interrupts

from UART channels A-D are wire-ORed internally to

function as a single IRQ interrupt. This pin transitions to a

logic 0 (if enabled by the interrupt enable register) whenever

a UART channel(s) requires service. Individual channel

interrupt status can be determined by addressing each

channel through its associated internal register, using CS

and A[3:4]. In the 68 mode, and external pull-up resistor

must be connected between this pin and V

. The function

of this pin changes to INTA when operating in the 16 mode

(see deﬁnition under INTA).

n.c. 21, 49,

52, 54,

55, 65

- - - - not connected

RESET,

RESET

37 27 20 J7 I Reset. In the 16 mode, a logic 1 on this pin will reset the

internal registers and all the outputs. The UART transmitter

output and the receiver input will be disabled during reset

time. (See

Section 7.11 “SC16C654B/654DB external reset

conditions” for initialization details.) When 16/68 is a logic 0

(68 mode), this pin functions similarly, but as an inverted

reset interface signal,

RESET.

Table 2: Pin description

…continued

Symbol Pin Type Description

PLCC68 LQFP64 HVQFN48 LFBGA6

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P58

SC16C654DBIB64,151

Mfr. #:

Buy SC16C654DBIB64,151

Manufacturer:

NXP Semiconductors

Description:

UART Interface IC 4CH. UART 64B FIFO

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SC16C654DBIB64,151

SC16C654DBIB64,151

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