SC16C654DBIB64,151 Datasheet SC16C654BIA68,518, SC16C654DBIB64,151, SC16C654BIBM,151 | P25-P27

Product data sheet Rev. 02 — 20 June 2005 25 of 58

Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7.1 Transmit (THR) and Receive (RHR) Holding Registers

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and

Transmit Shift Register (TSR). The status of the THR is provided in the Line Status

THR, providing that the THR or TSR is empty. The THR empty ﬂag in the LSR register will

be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR.

Note that a write operation can be performed when the THR empty ﬂag is set

(logic 0 = FIFO full; logic 1 = at least one FIFO location available).

The serial receive section also contains an 8-bit Receive Holding Register (RHR).

Receive data is removed from the SC16C654B/654DB and receive FIFO by reading the

RHR register. The receive section provides a mechanism to prevent false starts. On the

falling edge of a start or false start bit, an internal receiver counter starts counting clocks

at the 16× clock rate. After 7

⁄

clocks, the start bit time should be shifted to the center of

the start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated.

Evaluating the start bit in this manner prevents the receiver from assembling a false

character. Receiver status codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter

empty, line status and modem status registers. These interrupts would normally be seen

on the INTA to INTD output pins in the 16 mode, or on wire-OR IRQ output pin in the

68 mode.

Table 9: Interrupt Enable Register bits description

Bit Symbol Description

7 IER[7] CTS interrupt.

logic 0 = disable the CTS interrupt (normal default condition)

logic 1 = enable the CTS interrupt. The SC16C654B/654DB issues an

interrupt when the CTS pin transitions from a logic 0 to a logic 1.

6 IER[6] RTS interrupt.

logic 0 = disable the RTS interrupt (normal default condition)

logic 1 = enable the RTS interrupt. The SC16C654B/654DB issues an

interrupt when the RTS pin transitions from a logic 0 to a logic 1.

5 IER[5] Xoff interrupt.

logic 0 = disable the software ﬂow control, receive Xoff interrupt (normal

default condition)

logic 1 = enable the software ﬂow control, receive Xoff interrupt. See

Section

6.5 “Software ﬂow control” for details.

4 IER[4] Sleep mode.

logic 0 = disable Sleep mode (normal default condition)

logic 1 = enable Sleep mode. See

Section 6.11 “Sleep mode” for details.

3 IER[3] Modem Status Interrupt.

logic 0 = disable the modem status register interrupt (normal default

condition)

logic 1 = enable the modem status register interrupt

Product data sheet Rev. 02 — 20 June 2005 26 of 58

Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7.2.1 IER versus Receive FIFO interrupt mode operation

When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are

enabled, the receive interrupts and register status will reﬂect the following:

• The receive data available interrupts are issued to the external CPU when the FIFO

has reached the programmed trigger level. It will be cleared when the FIFO drops

below the programmed trigger level.

• FIFO status will also be reﬂected in the user accessible ISR register when the FIFO

trigger level is reached. Both the ISR register status bit and the interrupt will be cleared

when the FIFO drops below the trigger level.

• The data ready bit (LSR[0]) is set as soon as a character is transferred from the shift

7.2.2 IER versus Receive/Transmit FIFO polled mode operation

When FCR[0] = logic 1, resetting IER[0:3] enables the SC16C654B/654DB in the FIFO

polled mode of operation. Since the receiver and transmitter have separate bits in the

LSR, either or both can be used in the polled mode by selecting respective transmit or

receive control bit(s).

• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.

• LSR[1:4] will provide the type of errors encountered, if any.

• LSR[5] will indicate when the transmit FIFO is empty.

• LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.

• LSR[7] will indicate any FIFO data errors.

2 IER[2] Receive Line Status interrupt.

logic 0 = disable the receiver line status interrupt (normal default condition)

logic 1 = enable the receiver line status interrupt

1 IER[1] Transmit Holding Register interrupt. This interrupt will be issued whenever the

THR is empty, and is associated with LSR[1].

logic 0 = disable the transmitter empty interrupt (normal default condition)

logic 1 = enable the transmitter empty interrupt

0 IER[0] Receive Holding Register interrupt. This interrupt will be issued when the FIFO

has reached the programmed trigger level, or is cleared when the FIFO drops

below the trigger level in the FIFO mode of operation.

logic 0 = disable the receiver ready interrupt (normal default condition)

logic 1 = enable the receiver ready interrupt

Table 9: Interrupt Enable Register bits description

…continued

Bit Symbol Description

Product data sheet Rev. 02 — 20 June 2005 27 of 58

Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO

trigger levels, and select the DMA mode.

7.3.1 DMA mode

7.3.1.1 Mode 0 (FCR bit 3 = 0)

Set and enable the interrupt for each single transmit or receive operation, and is similar to

the 16C454 mode. Transmit Ready (TXRDY) will go to a logic 0 whenever an empty

transmit space is available in the Transmit Holding Register (THR). Receive Ready

(RXRDY) will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded with

a character.

7.3.1.2 Mode 1 (FCR bit 3 = 1)

Set and enable the interrupt in a block mode operation. The transmit interrupt is set when

the transmit FIFO is below the programmed trigger level. TXRDY remains a logic 0 as long

as one empty FIFO location is available. The receive interrupt is set when the receive

FIFO ﬁlls to the programmed trigger level. However, the FIFO continues to ﬁll regardless

of the programmed level until the FIFO is full. RXRDY remains a logic 0 as long as the

FIFO ﬁll level is above the programmed trigger level.

7.3.2 FIFO mode

Table 10: FIFO Control Register bits description

Bit Symbol Description

7:6 FCR[7] (MSB),

FCR[6] (LSB)

RCVR trigger. These bits are used to set the trigger level for the receive

FIFO interrupt.

An interrupt is generated when the number of characters in the FIFO

equals the programmed trigger level. However, the FIFO will continue to

be loaded until it is full. Refer to

Table 11.

5:4 FCR[5] (MSB),

FCR[4] (LSB)

TX trigger.

These bits are used to set the trigger level for the transmit FIFO

interrupt. The SC16C654B/654DB will issue a transmit empty interrupt

when the number of characters in FIFO drops below the selected trigger

level. Refer to

Table 12.

3 FCR[3] DMA mode select.

logic 0 = set DMA mode ‘0’ (normal default condition)

logic 1 = set DMA mode ‘1’

Transmit operation in mode ‘0’: When the SC16C654B/654DB is in

the 16C454 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO

mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when

there are no characters in the transmit FIFO or transmit holding register,

the

TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a

logic 1 after the ﬁrst character is loaded into the transmit holding

Receive operation in mode ‘0’: When the SC16C654B/654DB is in

mode ‘0’ (FCR[0] = logic 0), or in the FIFO mode (FCR[0] = logic 1;

FCR[3] = logic 0) and there is at least one character in the receive FIFO,

the

RXRDY pin will be a logic 0. Once active, the RXRDY pin will go to a

logic 1 when there are no more characters in the receiver.

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SC16C654DBIB64,151

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NXP Semiconductors

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UART Interface IC 4CH. UART 64B FIFO

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SC16C654DBIB64,151

SC16C654DBIB64,151

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