9397 750 14965 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 02 — 20 June 2005 14 of 58
Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6. Functional description
The SC16C654B/654DB provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data stream into
parallel data that is required with digital data systems. Synchronization for the serial data
stream is accomplished by adding start and stop bits to the transmit data to form a data
character. Data integrity is insured by attaching a parity bit to the data character. The
parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry
to provide all these functions is fairly complex, especially when manufactured on a single
integrated silicon chip. The SC16C654B/654DB represents such an integration with
greatly enhanced features. The SC16C654B/654DB is fabricated with an advanced
CMOS process to achieve low drain power and high speed requirements.
The SC16C654B/654DB is an upward solution that provides 64 bytes of transmit and
receive FIFO memory, instead of 16 bytes provided in the 16C554, or none in the 16C454.
The SC16C654B/654DB is designed to work with high speed modems and shared
network environments that require fast data processing time. Increased performance is
realized in the SC16C654B/654DB by the larger transmit and receive FIFOs. This allows
the external processor to handle more networking tasks within a given time. For example,
the SC16C554 with a 16-byte FIFO unloads 16 bytes of receive data in 1.53 ms. (This
example uses a character length of 11 bits, including start/stop bits at 115.2 kbit/s.) This
means the external CPU will have to service the receive FIFO at 1.53 ms intervals.
However, with the 64-byte FIFO in the SC16C654B/654DB, the data buffer will not require
unloading/loading for 6.1 ms. This increases the service interval, giving the external CPU
additional time for other applications and reducing the overall UART interrupt servicing
TXRDY39 - - - O Transmit Ready (active LOW). This function is associated
with the 68-pin package only.
TXRDY contains the
wire-ORed status of all four transmit channel FIFOs,
TXRDYA-TXRDYD. A logic 0 indicates a buffer ready status,
that is, at least one location is empty and available in one of
the TX channels (A to D). This pin goes to a logic 1 when all
four channels have no more empty locations in the TX FIFO
or THR. Individual channel TX status can be read by
examining individual internal registers via
CS and A[0:4] pin
functions.
V
CC
13, 47,
64
4, 21,
35, 52
2, 28 A8, B2,
J4, H10
I Power supply inputs.
XTAL1 35 25 18 J6 I Crystal or external clock input. Functions as a crystal
input or as an external clock input. A crystal can be
connected between this pin and XTAL2 to form an internal
oscillator circuit; see
Figure 10. Alternatively, an external
clock can be connected to this pin to provide custom data
rates; see
Section 6.9 “Programmable baud rate generator”.
XTAL2 36 26 19 K6 O Output of the crystal oscillator or buffered clock. (See
also XTAL1.) Crystal oscillator output or buffered clock
output.
Table 2: Pin description
…continued
Symbol Pin Type Description
PLCC68 LQFP64 HVQFN48 LFBGA6
4
