9397 750 14965 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 02 — 20 June 2005 40 of 58
Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
[1] Applies to external clock, crystal oscillator max 24 MHz.
[2] Maximum frequency =
[3] RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.
t
28d
delay from start to reset
TXRDY
-8T
RCLK
[3]
-8T
RCLK
[3]
-8T
RCLK
[3]
ns
t
30s
address setup time 10 - 10 - 10 - ns
t
30w
chip select strobe width 25 pF load
[1]
90 - 26 - 23 - ns
t
30h
address hold time 15 - 15 - 15 - ns
t
30d
read cycle delay 25 pF load 20 - 20 - 20 - ns
t
31d
delay from CS to data 25 pF load - 90 - 26 - 23 ns
t
31h
data disable time 25 pF load - 15 - 15 - 15 ns
t
32s
write strobe setup time 10 - 10 - 10 - ns
t
32h
write strobe hold time 10 - 10 - 10 - ns
t
32d
write cycle delay 25 - 25 - 20 - ns
t
33s
data setup time 20 - 15 - 15 - ns
t
33h
data hold time 15 - 5 - 5 - ns
t
RESET
RESET pulse width 200 - 40 - 40 - ns
N baud rate divisor 1 (2
16
− 1) 1 (2
16
− 1) 1 (2
16
− 1)
Table 28: Dynamic characteristics
…continued
T
amb
=
−
40
°
C to +85
°
C; tolerance of V
CC
=
±
10 %, unless otherwise specified.
Symbol Parameter Conditions V
CC
= 2.5 V V
CC
= 3.3 V V
CC
= 5.0 V Unit
Min Max Min Max Min Max
1
t
3w
-------
