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SC16C654DBIB64,151

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P58
9397 750 14965 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 02 — 20 June 2005 19 of 58
Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software flow control.
Different conditions can be set to detect Xon/Xoff characters and suspend/resume
transmissions. When double 8-bit Xon/Xoff characters are selected, the
SC16C654B/654DB compares two consecutive receive characters with two software flow
control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly.
Under the above described flow control mechanisms, flow control characters are not
placed (stacked) in the user accessible RX data buffer or FIFO.
In the event that the receive buffer is overfilling and flow control needs to be executed, the
SC16C654B/654DB automatically sends an Xoff message (when enabled) via the serial
TX output to the remote modem. The SC16C654B/654DB sends the Xoff1,2 characters
as soon as received data passes the programmed trigger level. To clear this condition, the
SC16C654B/654DB will transmit the programmed Xon1,2 characters as soon as receive
data drops below the programmed trigger level.
6.6 Special feature software flow control
A special feature is provided to detect an 8-bit character when EFR[5] is set. When 8-bit
character is detected, it will be placed on the user-accessible data stack along with normal
incoming RX data. This condition is selected in conjunction with EFR[0:3]. Note that
software flow control should be turned off when using this special mode by setting
EFR[0:3] to a logic 0.
The SC16C654B/654DB compares each incoming receive character with Xoff2 data. If a
match exists, the received data will be transferred to the FIFO, and ISR[4] will be set to
indicate detection of a special character. Although the Internal Register Table (Table 8)
shows each X-Register with eight bits of character information, the actual number of bits is
dependent on the programmed word length. Line Control Register bits LCR[0:1] define the
number of character bits, that is, either 5 bits, 6 bits, 7 bits or 8 bits. The word length
selected by LCR[0:1] also determine the number of bits that will be used for the special
character comparison. Bit 0 in the X-registers corresponds with the LSB bit for the receive
character.
6.7 Xon any feature
A special feature is provided to return the Xoff flow control to the inactive state following its
activation. In this mode, any RX character received will return the Xoff flow control to the
inactive state so that transmissions may be resumed with a remote buffer. This feature is
more fully defined in Section 6.5 “Software flow control”.
6.8 Hardware/software and time-out interrupts
Three special interrupts have been added to monitor the hardware and software flow
control. The interrupts are enabled by IER[5:7]. Care must be taken when handling these
interrupts. Following a reset, the transmitter interrupt is enabled, the SC16C654B/654DB
will issue an interrupt to indicate that the Transmit Holding Register is empty. This interrupt
must be serviced prior to continuing operations. The LSR register provides the current
singular highest priority interrupt only. It could be noted that CTS and RTS interrupts have
lowest interrupt priority. A condition can exist where a higher priority interrupt may mask
the lower priority CTS/RTS interrupt(s). Only after servicing the higher pending interrupt
will the lower priority CTS/TRS interrupt(s) be reflected in the status register. Servicing the
interrupt without investigating further interrupt conditions can result in data errors.
9397 750 14965 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 02 — 20 June 2005 20 of 58
Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt
priority (when enabled by IER[0]). The receiver issues an interrupt after the number of
characters have reached the programmed trigger level. In this case, the
SC16C654B/654DB FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The time-out
counter is reset at the center of each stop bit received or each time the receive holding
register (RHR) is read. The actual time-out value is 4 character time.
In the 16 mode for the PLCC68 package, the system/board designer can optionally
provide software controlled 3-state interrupt operation. This is accomplished by INTSEL
and MCR[3]. When INTSEL interface pin is left open or made a logic 0, MCR[3] controls
the 3-state interrupt outputs, INTA to INTD. When INTSEL is a logic 1, MCR[3] has no
effect on the INTA to INTD outputs, and the package operates with interrupt outputs
enabled continuously.
6.9 Programmable baud rate generator
The SC16C654B/654DB supports high speed modem technologies that have increased
input data rates by employing data compression schemes. For example, a 33.6 kbit/s
modem that employs data compression may require a 115.2 kbit/s input data rate.
A 128.0 kbit/s ISDN modem that supports data compression may need an input data rate
of 460.8 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable Baud Rate Generator is capable
of accepting an input clock up to 80 MHz (for 3.3 V and 5 V operation), as required for
supporting a 5 Mbit/s data rate. The SC16C654B/654DB can be configured for internal or
external clock operation. For internal clock oscillator operation, an industry standard
microprocessor crystal (parallel resonant/22 pF to 33 pF load) is connected externally
between the XTAL1 and XTAL2 pins; see Figure 10. Alternatively, an external clock can be
connected to the XTAL1 pin to clock the internal baud rate generator for standard or
custom rates; see Table 7.
The generator divides the input 16× clock by any divisor from 1 to (2
16
− 1). The
SC16C654B/654DB divides the basic external clock by 16. Further division of this 16×
clock provides two table rates to support low and high data rate applications using the
same system design. After a hardware reset and during initialization, the
Fig 10. Crystal oscillator connection
002aaa870
C2
47 pF
XTAL1 XTAL2
X1
1.8432 MHz
C1
22 pF
C2
33 pF
XTAL1 XTAL2
1.5 kΩ
X1
1.8432 MHz
C1
22 pF
9397 750 14965 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 02 — 20 June 2005 21 of 58
Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
SC16C654B/654DB sets the default baud rate table according to the state of the CLKSEL
pin. A logic 1 on CLKSEL will set the 1× clock default, whereas logic 0 will set the 4× clock
default table. Following the default clock rate selection during initialization, the rate tables
can be changed by the internal register MCR[7]. Setting MCR[7] to a logic 1 when
CLKSEL is a logic 1 provides an additional divide-by-4, whereas setting MCR[7] to a
logic 0 only divides by 1; see Table 7 and Figure 11. Customized baud rates can be
achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate
generator.
Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB) provides a
user capability for selecting the desired final baud rate. The example in Table 7 shows the
two selectable baud rate tables available when using a 7.3728 MHz crystal.
Table 7: Baud rate generator programming table using a 7.3728 MHz clock
Output baud rate User
16× clock divisor
DLM
program value
(HEX)
DLL
program value
(HEX)
MCR[7] = 1 MCR[7] = 0 Decimal HEX
50 200 2304 900 09 00
300 1200 384 180 01 80
600 2400 192 C0 00 C0
1200 4800 96 60 00 60
2400 9600 48 30 00 30
4800 19.2 k 24 18 00 18
9600 38.4 k 12 0C 00 0C
19.2 k 76.8 k 6 06 00 06
38.4 k 153.6 k 3 03 00 03
57.6 k 230.4 k 2 02 00 02
115.2 k 460.8 k 1 01 00 01
Fig 11. Baud rate generator circuitry
BAUD RATE
GENERATOR
LOGIC
BAUDOUT
MCR[7] = 1
MCR[7] = 0
DIVIDE-BY-1
LOGIC
DIVIDE-BY-4
LOGIC
CLOCK
OSCILLATOR
LOGIC
002aaa208
XTAL1
XTAL2
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SC16C654DBIB64,151

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Buy SC16C654DBIB64,151
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 4CH. UART 64B FIFO
Lifecycle:
New from this manufacturer.
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