SC16C654DBIB64,151 Datasheet SC16C654BIA68,518, SC16C654DBIB64,151, SC16C654BIBM,151 | P34-P36

Product data sheet Rev. 02 — 20 June 2005 34 of 58

Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7.8 Modem Status Register (MSR)

This register provides the current state of the control interface signals from the modem, or

other peripheral device to which the SC16C654B/654DB is connected. Four bits of this

whenever a control input from the modem changes state. These bits are set to a logic 0

whenever the CPU reads this register.

[1] Whenever any MSR bit 0:3 is set to logic 1, a Modem Status Interrupt will be generated.

Table 21: Modem Status Register bits description

Bit Symbol Description

7 MSR[7] CD (active HIGH, logical 1). Normally this bit is the complement of the

input. In the loop-back mode this bit is equivalent to the

OP2 bit in the MCR

6 MSR[6] RI (active HIGH, logical 1). Normally this bit is the complement of the

RI input.

In the loop-back mode this bit is equivalent to the

OP1 bit in the MCR register.

5 MSR[5] DSR (active HIGH, logical 1). Normally this bit is the complement of the

DSR

input. In loop-back mode this bit is equivalent to the

DTR bit in the MCR

4 MSR[4] CTS.

CTS functions as hardware ﬂow control signal input if it is enabled via

EFR[7]. The transmit holding register ﬂow control is enabled/disabled by

MSR[4]. Flow control (when enabled) allows starting and stopping the

transmissions based on the external modem

CTS signal. A logic 1 at the CTS

pin will stop SC16C654B/654DB transmissions as soon as current character

has ﬁnished transmission. Normally MSR[4] is the complement of the

CTS

input. However, in the loop-back mode, this bit is equivalent to the

RTS bit in

the MCR register.

3 MSR[3] ∆

[1]

logic 0 = no CD change (normal default condition)

logic 1 = the

CD input to the SC16C654B/654DB has changed state since

the last time it was read. A modem Status Interrupt will be generated.

2 MSR[2] ∆

[1]

logic 0 = no RI change (normal default condition)

logic 1 = the

RI input to the SC16C654B/654DB has changed from a logic 0

to a logic 1. A modem Status Interrupt will be generated.

1 MSR[1] ∆

DSR

[1]

logic 0 = no DSR change (normal default condition)

logic 1 = the

DSR input to the SC16C654B/654DB has changed state since

the last time it was read. A Modem Status Interrupt will be generated.

0 MSR[0] ∆

CTS

[1]

logic 0 = no CTS change (normal default condition)

logic 1 = the

CTS input to the SC16C654B/654DB has changed state since

the last time it was read. A Modem Status Interrupt will be generated.

Product data sheet Rev. 02 — 20 June 2005 35 of 58

Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7.9 Scratchpad Register (SPR)

The SC16C654B/654DB provides a temporary data register to store 8 bits of user

information.

7.10 Enhanced Feature Register (EFR)

Enhanced features are enabled or disabled using this register.

Bits 0 through 4 provide single or dual character software ﬂow control selection. When the

Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are

concatenated into two sequential numbers.

Table 22: Enhanced Feature Register bits description

Bit Symbol Description

7 EFR[7] Auto CTS. Automatic CTS Flow Control.

logic 0 = automatic CTS ﬂow control is disabled (normal default condition)

logic 1 = enable Automatic CTS ﬂow control. Transmission will stop when

CTS goes to a logical 1. Transmission will resume when the CTS pin

returns to a logical 0.

6 EFR[6] Auto RTS. Automatic RTS may be used for hardware ﬂow control by enabling

EFR[6]. When Auto RTS is selected, an interrupt will be generated when the

receive FIFO is ﬁlled to the programmed trigger level and

RTS will go to a

logic 1 at the next trigger level.

RTS will return to a logic 0 when data is

unloaded below the next lower trigger level. The state of this register bit

changes with the status of the hardware ﬂow control.

RTS functions normally

when hardware ﬂow control is disabled.

logic 0 = automatic RTS ﬂow control is disabled (normal default condition)

logic 1 = enable Automatic RTS ﬂow control

5 EFR[5] Special Character Detect.

logic 0 = special character detect disabled (normal default condition)

logic 1 = special character detect enabled. The SC16C654B/654DB

compares each incoming receive character with Xoff2 data. If a match

exists, the received data will be transferred to FIFO and ISR[4] will be set to

indicate detection of special character. Bit-0 in the X-registers corresponds

with the LSB bit for the receive character. When this feature is enabled, the

normal software ﬂow control must be disabled (EFR[3:0] must be set to a

logic 0).

4 EFR[4] Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4],

and MCR[7:5] can be modiﬁed and latched. After modifying any bits in the

enhanced registers, EFR[4] can be set to a logic 0 to latch the new values.

This feature prevents existing software from altering or overwriting the

SC16C654B/654DB enhanced functions.

logic 0 = disable (normal default condition)

logic 1 = enable

3:0 EFR[3:0] Cont-3:0 Tx, Rx control. Logic 0 or cleared is the default condition.

Combinations of software ﬂow control can be selected by programming these

bits. See

Table 23.

Product data sheet Rev. 02 — 20 June 2005 36 of 58

Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

[1] When using software ﬂow control the Xon/Xoff characters cannot be used for data transfer.

7.11 SC16C654B/654DB external reset conditions

Table 23: Software ﬂow control functions

[1]

Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software ﬂow controls

0 0 X X no transmit ﬂow control

1 0 X X transmit Xon1/Xoff1

0 1 X X transmit Xon2/Xoff2

1 1 X X transmit Xon1 and Xon2/Xoff1 and Xoff2

X X 0 0 no receive ﬂow control

X X 1 0 receiver compares Xon1/Xoff1

X X 0 1 receiver compares Xon2/Xoff2

1011transmit Xon1/Xoff1

receiver compares Xon1 and Xon2, Xoff1 and Xoff2

0111transmit Xon2/Xoff2

receiver compares Xon1 and Xon2/Xoff1 and Xoff2

1111transmit Xon1 and Xon2/Xoff1 and Xoff2

receiver compares Xon1 and Xon2/Xoff1 and Xoff2

Table 24: Reset state for registers

IER IER[7:0] = 0

ISR ISR[7:1] = 0; ISR[0] = 1

LCR LCR[7:0] = 0

MCR MCR[7:0] = 0

LSR LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0

MSR MSR[7:4] = input signals; MSR[3:0] = 0

FCR FCR[7:0] = 0

EFR EFR[7:0] = 0

Table 25: Reset state for outputs

Output Reset state

TXA, TXB, TXC, TXD HIGH

RTSA, RTSB, RTSC, RTSD HIGH

DTRA, DTRB, DTRC, DTRD HIGH

RXRDY HIGH

TXRDYLOW

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SC16C654DBIB64,151

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Manufacturer:

NXP Semiconductors

Description:

UART Interface IC 4CH. UART 64B FIFO

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SC16C654DBIB64,151

SC16C654DBIB64,151

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