SC16C654DBIB64,151 Datasheet SC16C654BIA68,518, SC16C654DBIB64,151, SC16C654BIBM,151 | P28-P30

Product data sheet Rev. 02 — 20 June 2005 28 of 58

Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

(cont.)

FCR[3]

(continued)

Transmit operation in mode ‘1’: When the SC16C654B/654DB is in

FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the

TXRDY pin will be a

logic 1 when the transmit FIFO is completely full. It will be a logic 0 when

the trigger level has been reached.

Receive operation in mode ‘1’: When the SC16C654B/654DB is in

FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has

been reached, or a Receive Time-Out has occurred, the

RXRDY pin will

go to a logic 0. Once activated, it will go to a logic 1 after there are no

more characters in the FIFO.

2 FCR[2] XMIT FIFO reset.

logic 0 = no FIFO transmit reset (normal default condition)

logic 1 = clears the contents of the transmit FIFO and resets the FIFO

counter logic (the transmit shift register is not cleared or altered). This

bit will return to a logic 0 after clearing the FIFO.

1 FCR[1] RCVR FIFO reset.

logic 0 = no FIFO receive reset (normal default condition)

logic 1 = clears the contents of the receive FIFO and resets the FIFO

counter logic (the receive shift register is not cleared or altered). This

bit will return to a logic 0 after clearing the FIFO.

0 FCR[0] FIFO enable.

logic 0 = disable the transmit and receive FIFO (normal default

condition)

logic 1 = enable the transmit and receive FIFO. This bit must be a ‘1’

when other FCR bits are written to, or they will not be

programmed.

Table 11: RX trigger levels

FCR[7] FCR[6] RX FIFO trigger level

0008

0116

1056

1160

Table 12: TX trigger levels

FCR[5] FCR[4] TX FIFO trigger level (# of characters)

0008

0116

1032

1156

Table 10: FIFO Control Register bits description

…continued

Bit Symbol Description

Product data sheet Rev. 02 — 20 June 2005 29 of 58

Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7.4 Interrupt Status Register (ISR)

The SC16C654B/654DB provides six levels of prioritized interrupts to minimize external

software interaction. The Interrupt Status Register (ISR) provides the user with six

interrupt status bits. Performing a read cycle on the ISR will provide the user with the

highest pending interrupt level to be serviced. No other interrupts are acknowledged until

the pending interrupt is serviced. Whenever the interrupt status register is read, the

interrupt status is cleared. However, it should be noted that only the current pending

interrupt is cleared by the read. A lower level interrupt may be seen after re-reading the

interrupt status bits. Table 13 “Interrupt source” shows the data values (bits 0:5) for the six

prioritized interrupt levels and the interrupt sources associated with each of these interrupt

levels.

Table 13: Interrupt source

Priority

level

ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt

1 000110LSR (Receiver Line Status

2 000100RXRDY (Receive Data

Ready)

2 001100RXRDY (Receive Data

time-out)

3 000010TXRDY (TransmitterHolding

4 000000MSR (Modem Status

5 010000RXRDY (Received Xoff

signal)/Special character

6 100000CTS, RTS change of state

Table 14: Interrupt Status Register bits description

Bit Symbol Description

7:6 ISR[7:6] FIFOs enabled. These bits are set to a logic 0 when the FIFO is not

being used. They are set to a logic 1 when the FIFOs are enabled.

logic 0 or cleared = default condition

5:4 ISR[5:4] INT priority bits 4:3. These bits are enabled when EFR[4] is set to a

logic 1. ISR[4] indicates that matching Xoff character(s) have been

detected. ISR[5] indicates that CTS, RTS have been generated. Note

that once set to a logic 1, the ISR[4] bit will stay a logic 1 until Xon

character(s) are received.

logic 0 or cleared = default condition

3:1 ISR[3:1] INT priority bits 2:0. These bits indicate the source for a pending

interrupt at interrupt priority levels 1, 2, and 3; see

Table 13.

Logic 0 or cleared = default condition.

0 ISR[0] INT status.

logic 0 = an interrupt is pending and the ISR contents may be used as

a pointer to the appropriate interrupt service routine

logic 1 = no interrupt pending (normal default condition)

Product data sheet Rev. 02 — 20 June 2005 30 of 58

Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication

format. The word length, the number of stop bits, and the parity are selected by writing the

appropriate bits in this register.

Table 15: Line Control Register bits description

Bit Symbol Description

7 LCR[7] Divisor latch enable. The internal baud rate counter latch and Enhance

Feature mode enable.

logic 0 = divisor latch disabled (normal default condition)

logic 1 = divisor latch and enhanced feature register enabled

6 LCR[6] Set break. When enabled, the Break control bit causes a break

condition to be transmitted (the TX output is forced to a logic 0 state).

This condition exists until disabled by setting LCR[6] to a logic 0.

logic 0 = no TX break condition (normal default condition)

logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the

remote receiver to a line break condition

5 LCR[5] Set parity. If the parity bit is enabled, LCR[5] selects the forced parity

format. Programs the parity conditions; see

Table 16.

logic 0 = parity is not forced (normal default condition)

LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1

for the transmit and receive data

LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0

for the transmit and receive data

4 LCR[4] Even parity. If the parity bit is enabled with LCR[3] set to a logic 1,

LCR[4] selects the even or odd parity format.

logic 0 = odd parity is generated by forcing an odd number of logic 1s

in the transmitted data. The receiver must be programmed to check

the same format (normal default condition).

logic 1 = even parity is generated by forcing an even number of

logic 1s in the transmitted data. The receiver must be programmed to

check the same format.

3 LCR[3] Parity enable. Parity or no parity can be selected via this bit.

logic 0 = no parity (normal default condition)

logic 1 = a parity bit is generated during the transmission, receiver

checks the data and parity for transmission errors

2 LCR[2] Stop bits. The length of stop bit is speciﬁed by this bit in conjunction with

the programmed word length; see

Table 17.

logic 0 or cleared = default condition

1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be

transmitted or received; see

Table 18.

logic 0 or cleared = default condition

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SC16C654DBIB64,151

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Manufacturer:

NXP Semiconductors

Description:

UART Interface IC 4CH. UART 64B FIFO

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SC16C654DBIB64,151

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