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BGW200EG_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 18 July 2007 16 of 76
NXP Semiconductors
BGW200EG
IEEE 802.11b System-in-Package
10.3 Hardware medium access control layer
Fig 6. HW MAC block diagram
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CRC
CHECKING
AND REMOVAL
802.11b
MODEM RX
INTERFACE
802.11b
MODEM TX
INTERFACE
MAC
HEADER
INSERTION
CRC
CALCULATION
AND INSERTION
THREE WIRE
BUS
INTERFACE
MAC HEADER
DECODING
RECEIVE
DMA
HW MAC
RX interrupt
HW MAC
TX interrupt
HW MAC
interrupt
TRANSMIT
DMA
RECEIVE CONTROL
TRANSMIT CONTROL
BTCX_WL
BTCX_BT
BTCX_PRI
BTCX_RXIND
MAC_CCA_OUT
RF_PA_ON
THW_CLK
THW_EN_N
THW_DATA
PHY Rx signals
PHY Tx signals
RF_TXRX
RF_TXRX_N
RF_TXRX_ANT
RF_ANT1_SEL
RF_ANT2_SEL
RF power detect
HW MAC CONTROL
AHB
BGW200EG_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 18 July 2007 17 of 76
NXP Semiconductors
BGW200EG
IEEE 802.11b System-in-Package
The IEEE 802.11b compliant HW MAC supports the following features:
Data rates up to 11 Mbit/s
SIFS timer
Cyclic Redundancy Check (CRC) calculation and checking
Back-off mechanism support
Automated transmit timing control
Automated TBTT/TXOP boundary checking
Automated NAV timer update
Automated IBSS mode beacon handling
Automated TSF update from the beacon packet
Automated insertion of TSF into the beacon packet
Automatic wake-up for beacon reception
Automated header field insertion (e.g. transmit address)
QoS support:
4 EDCF channels
2 streams for HCF
ATIM handler
SW programmable automated response mechanism (e.g. ACK, RTS, CTS and
QoS Null)
Programmable unicast, multicast and beacon filtering
Receive and transmit DMA engines for efficient data transfer
Configurable TX/RX status interrupts
Bluetooth coexistence Packet Traffic Arbitration (PTA) support
Configurable antenna TX/RX and diversity switch control signals
The HW MAC block has the following external interfaces:
SA2405 2.45 GHz transceiver control interface
Antenna, TX/RX and diversity switch control signals
Bluetooth coexistence interface
The HW MAC block has interfaces to the following subblocks:
Physical layer transmitter (PHYTX); see Section 10.7
Physical layer receiver (PHYRX); see Section 10.8
RF interface (RFIF); see Section 10.9
BGW200EG_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 18 July 2007 18 of 76
NXP Semiconductors
BGW200EG
IEEE 802.11b System-in-Package
10.4 WEP encryption and decryption coprocessor
The WEP encryption and decryption coprocessor has the following features:
WEP 64-bit and 128-bit encryption and decryption
WEP2 support in conjunction with firmware running on the microcontroller
MIC calculation to facilitate TKIP support in conjunction with firmware running on the
microcontroller
DMA controller for high data throughput with minimum processing load on the
microcontroller
Random number generator to assist in the generation of encryption keys
10.5 CCM encryption and decryption coprocessor
The CCM encryption and decryption coprocessor supports both the CCM (counter mode
with CBC-MAC) and the AES security algorithms. A DMA engine is incorporated to allow
high data throughput with minimum loading on the microcontroller.
Fig 7. Block diagram of the WEP encryption and decryption coprocessor
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WEP STATUS AND
CONTROL REGISTERS
RANDOM NUMBER
GENERATOR
WEP INTERRUPT
CONTROL
WEP
ENCRYPTION/
DECRYPTION
ENGINE
MIC
CALCULATION
ENGINE
DMA CONTROLLER
VPB
AHB
WEP interrupt
Fig 8. Block diagram of the CCM encryption and decryption coprocessor
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CCM STATUS AND
CONTROL REGISTERS
CCM INTERRUPT
CONTROL
CCM/AES
ENCRYPTION/
DECRYPTION
ENGINE
DMA CONTROLLER
VPB
AHB
CCM interrupt

BGW200EG/01,518

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC RF TXRX+MCU WIFI 68LFLGA
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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