BGW200EG_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 18 July 2007 47 of 76
NXP Semiconductors
BGW200EG
IEEE 802.11b System-in-Package
[1] Register definition is the same for all local scratch registers; replace n with the scratch register number (0 to 3).
[1] Register definition is the same for all host mailboxes; replace n with the mailbox number (0 to 3).
[2] Writing to this register generates an interrupt to the SDIO host if bit HMBn_INT_EN is set in register SD_HST_ISCR (see Table 49). A
host read clears the interrupt.
[1] Register definition is the same for all host scratch registers; replace n with the scratch register number (0 to 3).
Table 54. SD_LOC_SRn
[1]
register - SDIO local scratch register n (FN1 0 0128h to 0 0134h)
Legend: * reset value
Bit Symbol Access Value Description
Local Host
7 to 0 SCRCH_DATA[7:0] R R/W 00h* scratch data
Table 55. SD_HST_MBn
[1]
register - SDIO host mailbox n (FN1 0 013Ch to 0 0148h)
Legend: * reset value
Bit Symbol Access Value Description
Local Host
7 to 0 MBOX_DATA[7:0] R/W
[2]
R 00h* mailbox data
Table 56. SD_HST_SRn
[1]
register - SDIO host scratch register n (FN1 0 0150h to 0 015Ch)
Legend: * reset value
Bit Symbol Access Value Description
Local Host
7 to 0 SCRCH_DATA[7:0] R/W R 00h* scratch data
Table 57. SD_RST_CR register - SDIO reset control (FN1 0 0164h)
Legend: * reset value
Bit Symbol Access Value Description
Local Host
7 to 3 - R R 00h* reserved
2 SDIO_HOST_RST R/W R SDIO interface host side reset status
0* SDIO interface host side operational
1 SDIO interface host side reset ongoing
1 SDIO_FUNC_RST R/W R SDIO interface function side reset status
0* SDIO interface function side operational
1 SDIO interface function side reset ongoing
0 SA2443A_RST R R/W SA2443A reset control
0* do not reset SA2443A
1 reset SA2443A. A host write to this bit will result in
the SA2443A being reset.