BGW200EG_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 18 July 2007 46 of 76
NXP Semiconductors
BGW200EG
IEEE 802.11b System-in-Package
[1] Register definition is the same for all local mailboxes; replace n with the mailbox number (0 to 3).
[2] Writing to this register generates an interrupt to the local microcontroller if bit LMBn_INT_EN is set in register SD_LOC_ISCR; see
Table 48. A local read clears the interrupt.
4 H2F_DMA0_STAT R R host-to-function DMA channel 0 status
0* DMA idle
1 DMA transfer is ongoing
3 F2H_DMA_PEND1 R/W R function-to-host DMA channel 1 data pending status
0* no data pending
1 data pending
2 F2H_DMA_PEND0 R/W R function-to-host DMA channel 0 data pending status
0* no data pending
1 data pending
1 NEXT_F2H_CHAN R/W R DMA channel for next function-to-host transfer
0* TX DMA channel 0 will be used
1 TX DMA channel 1 will be used
0 NEXT_H2F_CHAN R/W R DMA channel for next host-to-function transfer
0* RX DMA channel 0 will be used
1 RX DMA channel 1 will be used
Table 50. SD_DMA_SCR register - SDIO DMA status and control (FN1 0 0108h)
…continued
Legend: * reset value
Bit Symbol Access Value Description
Local Host
Table 51. SD_H2F_DDAW register - SDIO host-to-function DMA data access window (FN1 0 010Ch)
Legend: * reset value
Bit Symbol Access Value Description
Local Host
7 to 0 DMA_DAW[7:0] - W 00h* host-to-function DMA data access window
Table 52. SD_F2H_DDAW register - SDIO function-to-host DMA data access window (FN1 0 0110h)
Legend: * reset value
Bit Symbol Access Value Description
Local Host
7 to 0 DMA_DAW[7:0] - R 00h* function-to-host DMA data access window
Table 53. SD_LOC_MBn
[1]
register - SDIO local mailbox n (FN1 0 0114h to 0 0120h)
Legend: * reset value
Bit Symbol Access Value Description
Local Host
7 to 0 MBOX_DATA[7:0] R R/W
[2]
00h* mailbox data
BGW200EG_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 18 July 2007 47 of 76
NXP Semiconductors
BGW200EG
IEEE 802.11b System-in-Package
[1] Register definition is the same for all local scratch registers; replace n with the scratch register number (0 to 3).
[1] Register definition is the same for all host mailboxes; replace n with the mailbox number (0 to 3).
[2] Writing to this register generates an interrupt to the SDIO host if bit HMBn_INT_EN is set in register SD_HST_ISCR (see Table 49). A
host read clears the interrupt.
[1] Register definition is the same for all host scratch registers; replace n with the scratch register number (0 to 3).
Table 54. SD_LOC_SRn
[1]
register - SDIO local scratch register n (FN1 0 0128h to 0 0134h)
Legend: * reset value
Bit Symbol Access Value Description
Local Host
7 to 0 SCRCH_DATA[7:0] R R/W 00h* scratch data
Table 55. SD_HST_MBn
[1]
register - SDIO host mailbox n (FN1 0 013Ch to 0 0148h)
Legend: * reset value
Bit Symbol Access Value Description
Local Host
7 to 0 MBOX_DATA[7:0] R/W
[2]
R 00h* mailbox data
Table 56. SD_HST_SRn
[1]
register - SDIO host scratch register n (FN1 0 0150h to 0 015Ch)
Legend: * reset value
Bit Symbol Access Value Description
Local Host
7 to 0 SCRCH_DATA[7:0] R/W R 00h* scratch data
Table 57. SD_RST_CR register - SDIO reset control (FN1 0 0164h)
Legend: * reset value
Bit Symbol Access Value Description
Local Host
7 to 3 - R R 00h* reserved
2 SDIO_HOST_RST R/W R SDIO interface host side reset status
0* SDIO interface host side operational
1 SDIO interface host side reset ongoing
1 SDIO_FUNC_RST R/W R SDIO interface function side reset status
0* SDIO interface function side operational
1 SDIO interface function side reset ongoing
0 SA2443A_RST R R/W SA2443A reset control
0* do not reset SA2443A
1 reset SA2443A. A host write to this bit will result in
the SA2443A being reset.
BGW200EG_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 18 July 2007 48 of 76
NXP Semiconductors
BGW200EG
IEEE 802.11b System-in-Package
[1] This bit will be cleared by a local read.
Table 58. SD_DMA_ISCR register - SDIO DMA interrupt status and control (FN1 0 0168h)
Legend: * reset value
Bit Symbol Access Value Description
Local Host
7 H2F1_INT_EN R/W R host-to-function DMA channel 1 interrupt control
0* interrupt disabled
1 interrupt will be generated on transfer completion
6 H2F0_INT_EN R/W R host-to-function DMA channel 0 interrupt control
0* interrupt disabled
1 interrupt will be generated on transfer completion
5 F2H1_INT_EN R/W R function-to-host DMA channel 1 interrupt control
0* interrupt disabled
1 interrupt will be generated on transfer completion
4 F2H0_INT_EN R/W R function-to-host DMA channel 0 interrupt control
0* interrupt disabled
1 interrupt will be generated on transfer completion
3 H2F1_INT_STAT R
[1]
R host-to-function DMA channel 1 interrupt status
0* no interrupt pending
1 transfer complete interrupt pending
2 H2F0_INT_STAT R
[1]
R host-to-function DMA channel 0 interrupt status
0* no interrupt pending
1 transfer complete interrupt pending
1 F2H1_INT_STAT R
[1]
R function-to-host DMA channel 1 interrupt status
0* no interrupt pending
1 transfer complete interrupt pending
0 F2H0_INT_STAT R
[1]
R function-to-host DMA channel 0 interrupt status
0* no interrupt pending
1 transfer complete interrupt pending
Table 59. SD_H2F_DSIZEL register - SDIO host-to-function DMA data size - lower byte (FN1 0 0198h)
Legend: * reset value
Bit Symbol Access Value Description
Local Host
7 to 0 DATA_SIZE[7:0] - R/W 00h* host-to-function DMA data size (lower byte)
Table 60. SD_H2F_DSIZEH register - SDIO host-to-function DMA data size - upper byte (FN1 0 019Ch)
Legend: * reset value
Bit Symbol Access Value Description
Local Host
7 to 0 DATA_SIZE[15:8] - R/W 00h* host-to-function DMA data size (upper byte)

BGW200EG/01,518

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC RF TXRX+MCU WIFI 68LFLGA
Lifecycle:
New from this manufacturer.
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