BGW200EG/01,518 Datasheet BGW200EG/01,518 | P28-P30

Product data sheet Rev. 01 — 18 July 2007 28 of 76

NXP Semiconductors

BGW200EG

IEEE 802.11b System-in-Package

The host mailboxes are written to by the SA2443A microcontroller and read from by the

host. A host interrupt is signaled on the SPI_EXT_INT pin when the microcontroller writes

to one of the host mailboxes.

Eight scratch registers are provided: 4 local registers (SPI2_LOC_SR0 to

SPI2_LOC_SR3; see Table 21) and 4 host registers (SPI2_HST_SR0 to SPI2_HST_SR3;

see Table 23). The scratch registers are accessed in the same way as the mailbox

registers, the only difference being that no interrupts are generated when the scratch

registers are written.

10.14.3 DMA controller

The DMA controller provides efﬁcient transfer of data between the host and SA2443A

internal memory. The host initiates all DMA transfers.

The DMA controller supports data transfers from 0 bytes to 65535 bytes.

10.14.4 Host SPI operations

The host can read or write registers in the SPI2 interface and initiate DMA transfers.

10.14.4.1 Write register command

The write register command is used by the host to write data into SPI interface registers.

It consists of one 16-bit packet. The command format is shown in Table 7.

10.14.4.2 Read register command

The read register command sequence is used by the host to read data from SPI interface

registers and consists of two packets:

• Read register initialization packet (16-bit, host-to-slave). The format of this packet is

shown in Table 8.

• Read data package (16-bit, slave-to-host). The format of this packet is shown in

Table 9.

Table 7. Write register command packet

Bit Symbol Value Description

15 COMMAND_TYPE 1h indicates a host-to-slave transfer

14 to 10 REG_ADDR[4:0] 00h to 1Ah see

Table 16 for valid register addresses

9 and 8 - - reserved

7 to 0 REG_DATA[7:0] 00h to FFh register data

Table 8. Read register command initialization packet

Bit Symbol Value Description

15 COMMAND_TYPE 0h indicates a slave-to-host transfer

14 to 10 REG_ADDR[4:0] 00h to 1Ah see

Table 16 for valid register addresses

9 to 0 - - reserved

Table 9. Read register command data packet

Bit Symbol Value Description

15 to 8 - - reserved

7 to 0 REG_DATA[7:0] 00h to FFh register data

Product data sheet Rev. 01 — 18 July 2007 29 of 76

NXP Semiconductors

BGW200EG

IEEE 802.11b System-in-Package

10.14.4.3 Host-to-slave DMA transfer

The host-to-slave DMA command sequence is used to transfer data from the host into

internal memory in the SA2443A and consists of the following packets:

• DMA initialization packet (16-bit, host-to-slave); see Table 10.

• DMA length packet (16-bit, host-to-slave); see Table 11.

• DMA data packets (8-bit, host-to-slave); see Table 12.

10.14.4.4 Slave-to-host DMA command sequence

The slave-to-host DMA command sequence is used to transfer data from SA2443A

internal memory to the host and consists of the following packets:

• DMA initialization packet (16-bit, slave-to-host); see Table 13.

• DMA length packet (16-bit, slave-to-host); see Table 14.

• DMA data packets (8-bit, slave-to-host); see Table 15.

Table 10. Host-to-slave DMA initialization packet

Bit Symbol Value Description

15 COMMAND_TYPE 1h indicates a host-to-slave transfer

14 to 10 INIT_CODE[4:0] 03h host-to-slave DMA initialization

9 to 0 - - reserved

Table 11. Host-to-slave DMA length packet

Bit Symbol Value Description

15 to 0 DATA_LEN[15:0] 0000h to FFFFh number of bytes to be transferred

Table 12. Host-to-slave DMA data packet

Bit Symbol Value Description

7 to 0 DATA[7:0] 00h to FFh DMA data

Table 13. Slave-to-host DMA initialization packet

Bit Symbol Value Description

15 COMMAND_TYPE 0h indicates a slave-to-host transfer

14 to 10 INIT_CODE[4:0] 04h slave-to-host DMA initialization

9 to 0 - - reserved

Table 14. Slave-to-host DMA length packet

Bit Symbol Value Description

15 to 0 DATA_LEN[15:0] 0000h to FFFFh number of bytes to be transferred

Table 15. Slave-to-host DMA data packet

Bit Symbol Value Description

7 to 0 DATA[7:0] 00h to FFh DMA data

Product data sheet Rev. 01 — 18 July 2007 30 of 76

NXP Semiconductors

BGW200EG

IEEE 802.11b System-in-Package

10.14.5 SPI2 registers

10.14.5.1 Register overview

10.14.5.2 Register details

Table 16. SPI2 registers

Local Host

SPI2_LOC_ISCR 00h R/W R local mailbox interrupt status and control

Table 17

SPI2_HST_ISCR 01h R R/W host mailbox interrupt status and control

Table 18

SPI2_DMA_SCR 02h R/W R DMA status and control register

Table 19

SPI2_LOC_MB0 05h R R/W local mailbox 0 (host-to-slave)

Table 20

SPI2_LOC_MB1 06h R R/W local mailbox 1 (host-to-slave)

SPI2_LOC_MB2 07h R R/W local mailbox 2 (host-to-slave)

SPI2_LOC_MB3 08h R R/W local mailbox 3 (host-to-slave)

SPI2_LOC_SR0 0Ah R R/W local scratch register 0 (host-to-slave)

Table 21

SPI2_LOC_SR1 0Bh R R/W local scratch register 1 (host-to-slave)

SPI2_LOC_SR2 0Ch R R/W local scratch register 2 (host-to-slave)

SPI2_LOC_SR3 0Dh R R/W local scratch register 3 (host-to-slave)

SPI2_HST_MB0 0Fh R/W R host mailbox 0 (slave-to-host)

Table 22

SPI2_HST_MB1 10h R/W R host mailbox 1 (slave-to-host)

SPI2_HST_MB2 11h R/W R host mailbox 2 (slave-to-host)

SPI2_HST_MB3 12h R/W R host mailbox 3 (slave-to-host)

SPI2_HST_SR0 14h R/W R host scratch register 0 (slave-to-host)

Table 23

SPI2_HST_SR1 15h R/W R host scratch register 1 (slave-to-host)

SPI2_HST_SR2 16h R/W R host scratch register 2 (slave-to-host)

SPI2_HST_SR3 17h R/W R host scratch register 3 (slave-to-host)

SPI2_RST_CR 19h R/W R/W reset control register

Table 24

SPI2_DMA_ISCR 1Ah R/W R DMA interrupt status and control

Table 25

Table 17. SPI2_LOC_ISCR register - SPI2 local mailbox interrupt status and control (00h)

Legend: * reset value

Bit Symbol Access Value Description

Local Host

7 LMB3_INT_EN R/W R local mailbox 3 interrupt control

0* do not generate interrupt when mailbox is written

1 generate interrupt when mailbox is written by the host

6 LMB2_INT_EN R/W R local mailbox 2 interrupt control

0* do not generate interrupt when mailbox is written

1 generate interrupt when mailbox is written by the host

5 LMB1_INT_EN R/W R local mailbox 1 interrupt control

0* do not generate interrupt when mailbox is written

1 generate interrupt when mailbox is written by the host

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P60 P61-P63 P64-P66 P67-P69 P70-P72 P73-P75 P76-P76

BGW200EG/01,518

Mfr. #:

Buy BGW200EG/01,518

Manufacturer:

NXP Semiconductors

Description:

IC RF TXRX+MCU WIFI 68LFLGA

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet

BGW200EG/01,518