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BGW200EG/01,518

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P76
BGW200EG_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 18 July 2007 31 of 76
NXP Semiconductors
BGW200EG
IEEE 802.11b System-in-Package
[1] This bit will be cleared following a local read.
4 LMB0_INT_EN R/W R local mailbox 0 interrupt control
0* do not generate interrupt when mailbox is written
1 generate interrupt when mailbox is written by the host
3 LMB3_INT_STAT R/W
[1]
R local mailbox 3 interrupt status
0* no interrupt pending
1 mailbox 3 interrupt pending
2 LMB2_INT_STAT R/W
[1]
R local mailbox 2 interrupt status
0* no interrupt pending
1 mailbox 2 interrupt pending
1 LMB1_INT_STAT R/W
[1]
R local mailbox 1 interrupt status
0* no interrupt pending
1 mailbox 1 interrupt pending
0 LMB0_INT_STAT R/W
[1]
R local mailbox 0 interrupt status
0* no interrupt pending
1 mailbox 0 interrupt pending
Table 17. SPI2_LOC_ISCR register - SPI2 local mailbox interrupt status and control (00h)
…continued
Legend: * reset value
Bit Symbol Access Value Description
Local Host
Table 18. SPI2_HST_ISCR register - SPI2 host mailbox interrupt status and control (01h)
Legend: * reset value
Bit Symbol Access Value Description
Local Host
7 HMB3_INT_EN R R/W host mailbox 3 interrupt control
0* do not generate interrupt when mailbox is written
1 generate interrupt when mailbox is written by the slave
6 HMB2_INT_EN R R/W host mailbox 2 interrupt control
0* do not generate interrupt when mailbox is written
1 generate interrupt when mailbox is written by the slave
5 HMB1_INT_EN R R/W host mailbox 1 interrupt control
0* do not generate interrupt when mailbox is written
1 generate interrupt when mailbox is written by the slave
4 HMB0_INT_EN R R/W host mailbox 0 interrupt control
0* do not generate interrupt when mailbox is written
1 generate interrupt when mailbox is written by the slave
3 HMB3_INT_STAT R R/W
[1]
host mailbox 3 interrupt status
0* no interrupt pending
1 mailbox 3 interrupt pending
2 HMB2_INT_STAT R R/W
[1]
host mailbox 2 interrupt status
0* no interrupt pending
1 mailbox 2 interrupt pending
BGW200EG_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 18 July 2007 32 of 76
NXP Semiconductors
BGW200EG
IEEE 802.11b System-in-Package
[1] This bit will be cleared following a host read.
1 HMB1_INT_STAT R R/W
[1]
host mailbox 1 interrupt status
0* no interrupt pending
1 mailbox 1 interrupt pending
0 HMB0_INT_STAT R R/W
[1]
host mailbox 0 interrupt status
0* no interrupt pending
1 mailbox 0 interrupt pending
Table 18. SPI2_HST_ISCR register - SPI2 host mailbox interrupt status and control (01h)
…continued
Legend: * reset value
Bit Symbol Access Value Description
Local Host
Table 19. SPI2_DMA_SCR register - SPI2 DMA status and control (02h)
Legend: * reset value
Bit Symbol Access Value Description
Local Host
7 S2H_DMA1_STAT R R slave-to-host DMA channel 1 status
0* DMA idle
1 DMA transfer is ongoing
6 S2H_DMA0_STAT R R slave-to-host DMA channel 0 status
0* DMA idle
1 DMA transfer is ongoing
5 H2S_DMA1_STAT R R host-to-slave DMA channel 1 status
0* DMA idle
1 DMA transfer is ongoing
4 H2S_DMA0_STAT R R host-to-slave DMA channel 0 status
0* DMA idle
1 DMA transfer is ongoing
3 S2H_DMA_PEND1 R/W R slave-to-host DMA channel 1 data pending status
0* no data pending
1 data pending
2 S2H_DMA_PEND0 R/W R slave-to-host DMA channel 0 data pending status
0* no data pending
1 data pending
1 NEXT_S2H_CHAN R/W R DMA channel to be used for next slave-to-host transfer
0* TX DMA channel 0 will be used
1 TX DMA channel 1 will be used
0 NEXT_H2S_CHAN R/W R DMA channel to be used for next host-to-slave transfer
0* RX DMA channel 0 will be used
1 RX DMA channel 1 will be used
BGW200EG_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 18 July 2007 33 of 76
NXP Semiconductors
BGW200EG
IEEE 802.11b System-in-Package
[1] Register definition is the same for all local mailboxes; replace n with the mailbox number (0 to 3).
[2] Writing to this register generates an interrupt to the local microcontroller if bit LMBn_INT_EN is set in register SPI2_LOC_ISCR (see
Table 17). A local read clears the interrupt.
[1] Register definition is the same for all local scratch registers; replace n with the scratch register number (0 to 3).
[1] Register definition is the same for all host mailboxes; replace n with the mailbox number (0 to 3).
[2] Writing to this register generates an interrupt to the SPI host if bit HMBn_INT_EN is set in register SPI2_HST_ISCR; see Table 18. A
host read clears the interrupt.
[1] Register definition is the same for all host scratch registers; replace n with the scratch register number (0 to 3).
Table 20. SPI2_LOC_MBn
[1]
register - SPI2 local mailbox n (05h to 08h)
Legend: * reset value
Bit Symbol Access Value Description
Local Host
7 to 0 MBOX_DATA[7:0] R R/W
[2]
00h* mailbox data
Table 21. SPI2_LOC_SRn
[1]
register - SPI2 local scratch register n (0Ah to 0Dh)
Legend: * reset value
Bit Symbol Access Value Description
Local Host
7 to 0 SCRCH_DATA[7:0] R R/W 00h* scratch data
Table 22. SPI2_HST_MBn
[1]
register - SPI2 host mailbox n (Fh to 12h)
Legend: * reset value
Bit Symbol Access Value Description
Local Host
7 to 0 MBOX_DATA[7:0] R/W
[2]
R 00h* mailbox data
Table 23. SPI2_HST_SRn
[1]
register - SPI2 host scratch register n (14h to 17h)
Legend: * reset value
Bit Symbol Access Value Description
Local Host
7 to 0 SCRCH_DATA[7:0] R/W R 00h* scratch data
Table 24. SPI2_RST_CR register - SPI2 reset control (19h)
Legend: * reset value
Bit Symbol Access Value Description
Local Host
7 to 3 - R R 00h* reserved
2 SPI2_HOST_RST R/W R SPI2 interface host side reset status
0* SPI2 interface host side operational
1 SPI2 interface host side reset ongoing
1 SPI2_SLAVE_RST R/W R SPI2 interface slave side reset status
0* SPI2 interface slave side operational
1 SPI2 interface slave side reset ongoing
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P76

BGW200EG/01,518

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Buy BGW200EG/01,518
Manufacturer:
NXP Semiconductors
Description:
IC RF TXRX+MCU WIFI 68LFLGA
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New from this manufacturer.
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