BGW200EG_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 18 July 2007 27 of 76
NXP Semiconductors
BGW200EG
IEEE 802.11b System-in-Package
10.14.1 SPI interface
The SPI interface operates entirely in the SPI clock domain. This enables the use of a
higher SPI clock frequency than would be allowed with the usual oversampling scheme.
SPI2 clock frequencies of up to 66 MHz are allowed.
The SPI_SCK for SPI2 only needs to run when a data transfer is in progress. No
additional clock pulses are needed.
When the SA2443A is the only slave on the SPI bus the SPI_SS_N signal can be tied
permanently LOW, without any impact on power consumption.
The SPI interface supports mode 3 slave operation. The relationship between SPI_SCK,
SPI_MOSI and SPI_MISO is illustrated in Figure 18. Data on SPI_MOSI is sampled on
the rising edge of SPI_SCK. The SA2443A can be programmed (by firmware running on
the SA2443A microcontroller) to transition SPI_MISO on either the falling edge or rising
edge of SPI_SCK.
Care should be taken that none of the SPI interface signals are driven HIGH when V
DDA
is
lower than the minimum recommended operating voltage; see Table 66.
The write register command and all initialization packets are always sent MSB first. The bit
order of the read register data, DMA size and DMA data packets can be programmed (by
firmware running on the SA2443A microcontroller) to allow either the LSB or the MSB in a
packet to be transferred first.
10.14.2 Mailboxes and scratch registers
The SPI2 interface contains 8 mailboxes: 4 local mailboxes (SPI2_LOC_MB0 to
SPI2_LOC_MB3; see Table 20) and 4 host mailboxes (SPI2_HST_MB0 to
SPI2_HST_MB3; see Table 22).
The local mailboxes are written to by the host and read from by the SA2443A
microcontroller. A local SPI2 interrupt is generated when the host writes to one of the local
mailboxes. The enabling of generation of the interrupt is programmable.
Fig 18. SPI2 timing diagram
001aad203
SPI_SCK
SPI_SS_N
SPI_MOSI
(input)
SPI_MISO
(output)
