BGW200EG_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 18 July 2007 20 of 76
NXP Semiconductors
BGW200EG
IEEE 802.11b System-in-Package
The test modes available with the PHYTX block and their uses are given in Table 5.
10.8 Physical layer receiver
The PHYRX block is IEEE 802.11b compliant and supports the following features:
• 1 Mbit/s, 2 Mbit/s, 5.5 Mbit/s and 11 Mbit/s data rates
• Short and long preambles
• Decision feedback equalizer with > 200 ns RMS multipath delay spread tolerance
• Antenna diversity
The PHYRX block is tightly coupled to the SA2443A HW MAC block; see Section 10.3.
Control and configuration of the PHYRX block is performed by the HW MAC block and
firmware. The PHYRX also interfaces to the RF interface block; see Section 10.9.
The RX controller contains the state machine that switches the modes of the RX blocks
and performs the following functions:
• Clear Channel Assessment (CCA)
• Bit synchronization
• Antenna diversity
The fine AGC block adjusts the received signal level for optimum receiver performance.
Sampling clock correction and carrier frequency correction are handled by the chip clock
recovery and carrier recovery blocks respectively. Correction for multipath distortion is
performed by a fractionally spaced decision feedback equalizer.
Table 5. PHYTX test modes
Test mode Description Measurement uses
RANDOM continuous modulated random data EVM, spectral mask
0101 continuous 0101 sequence carrier suppression
CW unmodulated I/Q data transmit frequency offset
Fig 11. Block diagram of the physical layer receiver
001aad196
DEMODULATOR EQUALIZER
RX CONTROLLER
CARRIER
RECOVERY
CHIP CLOCK
RECOVERY
FINE AGC
RFIF
data signals
RFIF
control signals
RF_AGC_RST
RF_AGC_SET
RF_ANT_DIV
RX data
RX control
signals
block
control
signals
