BGW200EG_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 18 July 2007 22 of 76
NXP Semiconductors
BGW200EG
IEEE 802.11b System-in-Package
10.10 System timers
The SA2443A contains five general-purpose timers and a WatchDog Timer (WDT).
Table 6 provides an overview of the timer functionality.
Timers 0, 1, 3 and 4 can be programmed with a start value. Operation can be either single
shot or continuous. An interrupt is generated when a timer counts down to zero.
Timer 2 is programmed with up to four interrupt compare values. An interrupt is generated
when the counter value matches one of the interrupt compare values. Operation can be
either one shot or continuous.
The watchdog timer provides a mechanism to reset the SA2443A if for some reason the
firmware becomes locked. A start value is programmed from which the counter counts
down to zero. For correct operation of the SA2443A the firmware must reset the start
value before the counter reaches zero. If the counter reaches zero the SA2443A is reset.
An interrupt compare value can be programmed, allowing a warning to be generated prior
to the full reset.
Fig 13. Block diagram of system timers
Table 6. Timer overview
Timer name Type Count
frequency
Interrupt conditions
TIMER0 down count bus clock on zero
TIMER1 down count bus clock on zero
TIMER2 up count 1 MHz when count matches any of four programmed
values
TIMER3 down count 1 MHz on zero
TIMER4 down count 1 MHz on zero
WDT down count 1 MHz interrupt when count matches programmed
value; reset generated when count reaches zero
001aad198
T2 interrupt 1
T0 interrupt
T2 interrupt 2
T2 interrupt 3
T2 interrupt 4
TIMER0
T1 interrupt
TIMER1
T3 interrupt
T4 interrupt
WDT interrupt
WDT reset
TIMER3
TIMER2
TIMER4
WATCHDOG
TIMER
VPB
1 MHz
bus clock
