BGW200EG_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 18 July 2007 58 of 76
NXP Semiconductors
BGW200EG
IEEE 802.11b System-in-Package
14.3 Clock and reset
Table 71. Dynamic characteristics for clock and reset signals
Symbol Parameter Conditions Min Typ Max Unit
Reference clock; see
Figure 29
f
clk(ref)
reference clock frequency 43.9889 44.0000 44.0011 MHz
t
wH(clk)(ref)
reference clock HIGH pulse width 10.5 - - ns
t
wL(clk)(ref)
reference clock LOW pulse width 10.5 - - ns
Sleep clock; see
Figure 30
f
clk(sleep)
sleep clock frequency 28 32 1000 kHz
t
wH(clk)(sleep)
sleep clock HIGH pulse width 50.0 - - ns
t
wL(clk)(sleep)
sleep clock LOW pulse width 50.0 - - ns
Reset; see
Figure 31
t
wL(RST_N)
RST_N LOW pulse width 10.0 - - ns
Power-on reset; see
Figure 32
V
POR
power-on reset voltage - 1.3 - V
t
wL(POR)
power-on reset LOW pulse width
time
3.5 4.0 4.7 ms
Fig 29. 44 MHz reference clock timing
Fig 30. Sleep clock timing
Fig 31. Reset timing
001aad221
f
clk(ref)
t
wH(clk)(ref)
t
wL(clk)(ref)
001aad222
f
clk(sleep)
t
wH(clk)(sleep)
t
wL(clk)(sleep)
001aad223
RST_N
t
wL(RST_N)
BGW200EG_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 18 July 2007 59 of 76
NXP Semiconductors
BGW200EG
IEEE 802.11b System-in-Package
14.4 SPI1 interface
Fig 32. Power-on reset timing
V
POR
001aad224
POR_N
V
POR
t
wL(POR)
Table 72. Dynamic characteristics for SPI1
Symbol Parameter Conditions Min Typ Max Unit
SPI clock input; see
Figure 33
T
SPI_SCK
SPI_SCK period 120.0 - - ns
t
clk(H)
clock HIGH time 50.0 - - ns
t
clk(L)
clock LOW time 50.0 - - ns
SPI slave select input; see
Figure 35 and Figure 36
t
su(SPI_SS_N)
SPI_SS_N set-up time 100.0 - - ns
t
h(SPI_SS_N)
SPI_SS_N hold time 100.0 - - ns
SPI_MOSI output; see
Figure 33 and Figure 34;
t
d(o)(SPI_MOSI)
SPI_MOSI output delay time C
L
= 10 pF - - 5.0 ns
t
h(o)(SPI_MOSI)
SPI_MOSI output hold time C
L
= 10 pF 1.0 - - ns
SPI_MOSI input; see
Figure 35 and Figure 36
t
su(SPI_MOSI)
SPI_MOSI set-up time 3.0 - - ns
t
h(i)(SPI_MOSI)
SPI_MOSI input hold time 2.0 - - ns
SPI_MISO output; see
Figure 35 and Figure 36
t
en(o)(SPI_MISO)
SPI_MISO output enable time C
L
= 10 pF - - 10.0 ns
t
dis(o)(SPI_MISO)
SPI_MISO output disable time C
L
= 10 pF - - 10.0 ns
t
d(o)(SPI_MISO)
SPI_MISO output delay time C
L
= 10 pF - - 100.0 ns
t
h(o)(SPI_MISO)
SPI_MISO output hold time C
L
= 10 pF 0.0 - - ns
SPI_MISO input; see
Figure 33 and Figure 34
t
su(SPI_MISO)
SPI_MISO set-up time 20.0 - - ns
t
h(i)(SPI_MISO)
SPI_MISO input hold time 5.0 - - ns
BGW200EG_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 18 July 2007 60 of 76
NXP Semiconductors
BGW200EG
IEEE 802.11b System-in-Package
Fig 33. SPI1 master timing (CPHA = 0)
Fig 34. SPI1 master timing (CPHA = 1)
t
clk(H)
t
clk(L)
t
d(o)(SPI_MOSI)
t
h(o)(SPI_MOSI)
t
su(SPI_MISO)
t
h(i)(SPI_MISO)
T
SPI_SCK
001aad225
SPI_SCK
(CPOL = 0)
SPI_SCK
(CPOL = 1)
SPI_SS_N
SPI_MOSI
(output)
SPI_MISO
(input)
t
su(SPI_MISO)
t
h(i)(SPI_MISO)
t
d(o)(SPI_MOSI)
t
h(o)(SPI_MOSI)
T
SPI_SCK
001aad226
SPI_MOSI
(output)
SPI_MISO
(input)
SPI_SCK
(CPOL = 0)
SPI_SCK
(CPOL = 1)
SPI_SS_N

BGW200EG/01,518

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NXP Semiconductors
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IC RF TXRX+MCU WIFI 68LFLGA
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