13
AT49LD3200(B)
1940B–FLASH–11/01
Latency There are latencies between the issuance of a Row Active command and when data is
available on the I/O buffers. The RAS
to CAS delay is defined as the RAS latency. The
CAS to data out delay is the CAS latency. The CAS and RAS latencies are programma-
ble through the mode register. RAS latencies of 1 and 2, and CAS latencies of 2 through
6 are supported. It is understood that some RAS and CAS latency values are reserved
for future use, and are not available in this generation of synchronous Flash. The follow-
ing are the supported minimum values: RAS latency = 2, and CAS latency = 6 for 100
MHz operation, and RAS latency = 2, and CAS latency = 5 for 66 MHz operation, and
RAS latency = 1, and CAS latency = 4 for 50 MHz operation, and RAS latency = 1, and
CAS latency = 3 for 33 MHz operation.
DQM Operation The DQM is used to mask output operations when a complete burst read is not required.
It works similar to OE
during a read operation. The read latency is two cycles from DQM,
which means DQM masking occurs two cycles later in the read cycle. DQM operation is
synchronous with the clock. The masking occurs for a complete cycle. (Also refer to the
DQM timing diagram.)
Burst Read The Burst Read command is used to access a burst of data on consecutive clock cycles
from an active row state. The Burst Read command is issued by asserting low CS
and
CAS
with MR being high on the rising edge of the clock. The first output appears in CAS
latency number of clock cycles after the issuance of the Burst Read command. The
burst length, burst sequence and latency from the Burst Read command are determined
by the mode register, which is already programmed. Burst read can be initiated on any
column address of the active row. The output goes into high-impedance at the end of
the burst, unless a new burst read is initiated to keep the data output gapless. The burst
read can be terminated by issuing another burst read.
Sector Erase Before a word/double word can be reprogrammed, it must be erased. The erased state
of the memory bits is a logical “1”. The AT49LD3200(B) is organized into eight uniform
four megabit sectors (SA0 - SA7) that can be individually erased. The Sector Erase
command is a synchronous six-bus cycle operation (refer to the Command Definition
table and Program Cycle and Erase Cycle waveforms). The erase code consists of 6-
byte (DQ8 - DQ31 are Don’t Care inputs for the command) load commands to specific
address locations with a specific data pattern. The sector address and 30H data input
are latched in the sixth cycle. The sector erase starts at the following rising edge of CLK
after the sixth cycle. The erase operation is internally controlled; it will automatically time
to completion.
Any commands written to the device during the erase cycle will be ignored. The maxi-
mum time needed to erase one sector is t
EC
.
Word/Double Word
Programming
Once a sector is erased, it is programmed (to a logical “0”) on a word-by-word/double-
word-by-double-word basis. Programming is accomplished via the internal device com-
mand register and is synchronous four-bus cycle operation (refer to the Command
Definition table and Program Cycle and Erase Cycle waveforms). The programming
operation starts at the following rising edge of CLK after the fourth cycle. The device will
automatically generate the required internal program pulses.
Any commands written to the device during the embedded programming cycle will be
ignored. Please note that a data “0” cannot be programmed back to a “1”; only erase
operations can convert “0”s to “1”s. Programming is completed after the specified t
PGM
cycle time. The DATA polling feature may also be used to indicate the end of a program
cycle.
