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AT49LD3200-13TC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39
7
AT49LD3200(B)
1940B–FLASH–11/01
Notes: 1. These t
RC
values are for BL = 8. For BL = 4, t
RC
= 7 CLKs for up to 100 MHz, t
RC
= 6 CLKs for up to 75 MHz, t
RC
= 5 CLKs for
up to 50 MHz. RAS latency increase means a simultaneous t
RC
increase in the same number of cycles. (If RAS latency is
3CLKs, t
RC
is 12 CLKs for BL = 8.) Refer to page 27 for gapless operation.
2. These t
VCVC
values are for BL = 8. For BL = 4, t
VCVC
= 5 CLKs for up to 100 MHz, t
VCVC
= 4 CLKs for up to 75 MHz,
t
VCVC
= 3 CLKs for up to 50 MHz. Refer to page 27 for gapless operation.
AC Read Characteristics
AC operating conditions unless otherwise noted.
Symbol Parameter
<
100 MHz <75 MHz <50 MHz
UnitsMin Max Min Max Min Max
t
CC
CLK Cycle Time 10 13 20 ns
t
SAC
CLK to Valid Output Delay 7 8 9 ns
t
OH
Data Output Hold Time 3 4 4 ns
t
CH
CLK High Pulse Width 3 4 6.5 ns
t
CL
CLK Low Pulse Width 3 4 6.5 ns
t
RC
Row-active to Row-active
(1)
11 10 9 clks
t
SS
Input Setup Time 2 4 4 ns
t
SH
Input Hold Time 1 2 2 ns
t
SLZ
CLK to Output in Low-Z 0 0 0 ns
t
SHZ
CLK to Output in High-Z 7 10 15 ns
t
T
Transition Time 0.1 10 0.1 10 0.1 10 ns
t
VCVC
Valid CAS Enable to Valid CAS Enable
(2)
9 8 7 clks
8
AT49LD3200(B)
1940B–FLASH–11/01
Notes: 1. A
0
~ A
6
: Program keys (@MRS). After power-up, mode register set can be set before issuing other input command. After the
Mode Register Set command is completed, no new commands can be issued for 3 CLK Cycles, and CS
or MR state must
be defined “H” within 3 CLK cycles. Refer to the Mode Register Control Table.
2. In the case CKE is low, two standby modes are possible. Those are standby mode in power-down, and active standby mode
in clock suspend (non-power-down).
Power-down: CKE = “L” (after no command is issued for 60 µs)
Clock Suspend: CKE = “L” (at the range of Row Active, Read and Data Out)
3. DQM sampled at rising edge of a CLK makes a high-Z state the data-out state, delayed by 2 CLK cycles.
4. Precharge command on Synch. DRAM can be used for Burst Stop operation during burst read operation only.
5. Mode selection is controlled by the polarity of WORD
pin, “H” state is DWM, “L” state is WM. WORD should be set to the
desired state during power-up and prior to any device operation.
6. Data is provided through DQ
0
~ DQ
31
. Refer to AC programming and erasing waveforms.
7. DQ
0
~ DQ
31
will output Manufacturer Code/Device Code.
8. A
0
= A
2
= A
11
= “H”, A
1
= A
10
= A
12
= “L”
9. The user can tie MR
and WE together to simplify the interface of the AT49LD3200(B) onto the standard SDRAM bus.
Function Truth Table
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Abbreviations (RA: Row Address, CA: Column Address, NOP: No Operation Command, DWM: Double Word Mode, WM:
Word Mode)
Command CKEn-1 CKEn CS RAS CAS MR
(9)
DQM Add. WORD VPP WE
Register
(1)
Mode Register Set H X L L L L X Code X X X
Row Active
Row Access
& Latch
HXLLHHXRAXXX
Read
Column Access
& Latch
HXLHLHXCAXXH
Burst Stop
HXLHHLXXXXX
(Precharge on
Synch. DRAM)
HXLLHLXXXXX
Power-down
and Clock
Suspend
(2)
Two
Standby
Mode
Entry H L X X X X X X X X X
Exit L H X X X X X X X X X
DQM
(3)
HXXXXXVXXXX
No Operation Command
(4)
HXHXXXXXXXX
HXLHHHXXXXX
Organization Control
(5)
HXLHLHXCA
H
XH
L
Program/Erase
(6)
HXLHLXXCAXXL
Fast Program/Erase
(6)
HXLHLXXCAX12VL
Program/Erase Inhibit H X H X X X X X X X X
Product
Identification
(7)
Mode Register Set H X L L L L X A
7
= H X X X
Read H X L H L H X L X X H
Continuity Test Mode
Entry H X L H L X X CA X X L
Exit X X X X X X X Code
(8)
XXX
9
AT49LD3200(B)
1940B–FLASH–11/01
Notes: 1. Program/Erase is performed through the synchronous bus cycle operation after the boot block is activated through either
power-up or Mode Register Set.
2. It is recommended to hold CKE Low if CLK is running during asynchronous boot block mode except for synchronous com-
mand cycle and MRS operations.
Note: 1. After power-up, when the user wants to change Mode Register Set, the user must exit from power-down mode and start
Mode Register Set before entering normal operation mode. Reserved modes are not to be used; device function in these
modes is not guaranteed.
Asynchronous Boot Block Function Truth Table
Command CLK
(2)
CKE
(2)
CS RAS CAS MR DQM Add. WORD VPP WE
Read X X L X X X L Add X X X
Output Disable XXLXXXHXXXX
Program/Erase
(1)
HLHLXXAddXXL
Fast Program/Erase
(1)
HLHLXXAddX12VL
Program/Erase Inhibit H H X X X X X X X X
Mode Register Control Table
(1)
Register Programmed with MRS
Address A7 A6 A5 A4 A3 A2 A1 A0
Function Product ID RAS Latency CAS Latency Burst Type Burst Length
Product ID RAS Latency CAS Latency Burst Type Burst Length
A7 “Read” A6 Type A5 A4 A3 Length A2 Type A1 A0 Length
0 Array 0 1 0 0 0 Reserved 0 Sequential 0 0 Reserved
1 ID 1 2 001 2 1 Interleave 0 1 4
010 3 1 0 8
011 4 1 1 Boot Block
100 5
101 6
110 7
111 8
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39

AT49LD3200-13TC

Mfr. #:
Buy AT49LD3200-13TC
Manufacturer:
Microchip Technology / Atmel
Description:
NOR Flash 32M bit
Lifecycle:
New from this manufacturer.
Delivery:
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