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AT49LD3200-13TC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39
25
AT49LD3200(B)
1940B–FLASH–11/01
Mode Register Set: @RAS Latency = 2, CAS Latency = 5, Burst Length = 4
Notes: 1. After the Mode Register Set is completed, no new commands can be issued for 3 CLK cycles.
2. After power-up, necessarily Mode Register Set should be completed at least one time and CS
or MR must be fixed “H” within
3 clock cycles, and when user wants to change Mode Register Set, user must exit from power-down mode and start Mode
Register Set before chip enters normal operation mode.
012345678910111213141516171819
t
SS
t
SH
CKE
CS
RAS
CAS
ADDR
Data
MR
t
CH
t
CC
t
CL
HIGH
Code
RAa
Data High-Z State
MRS Row Active
: Don't Care
CAa
DQa0 DQa1 DQa2 DQa3
CLK
26
AT49LD3200(B)
1940B–FLASH–11/01
Note: 1. After the power-up, when user wants to change MR Set, user must exit from power-down mode and start MR Set before chip
enters normal operation mode.
Detailed Functional Truth Table
Current
State
Input Signal
Next State OperationCKE CS
RAS CAS MR Add.
After
Power-up
(1)
LXXXXXPower-down
H L L H H RA Row Active; latch RA
HLLLLCodeMode Register Set
Row Active
HLLHHRA
If consecutive row access is issued within t
RC
(min.)
without CAS
enabling, only the final RA is valid.
H L H L H CA Begin READ; latch CA
HLLLLCodeIllegal
(1)
L XXXXXClock Suspend
READ
HLLHHRA
Row Access in Read State, within the t
RC
, previous
read is ignored and new row is activated. Beyond the
t
RC
, previous read is completed and new read
begins.
HLHLHCA
Consecutive Column Access, within the t
VCVC
, only
the final CA is valid and the previous burst read is
ignored. Beyond the t
VCVC
, the previous read is
completed and new read begins.
H L L H L X NOP (after Burst Read)/Read Interrupt
H L H H L X NOP (after Burst Read)/Read Interrupt
HLLLLCodeIllegal
(1)
LXXXXXClock Suspend/Power-down
Any StateLLLLHXLow Power Consumption Mode
Any State H L H H H X NOP
Any State
HLLLHXIllegal
H L H L L CA Illegal
27
AT49LD3200(B)
1940B–FLASH–11/01
Technical Notes
Frequency vs. AC Parameter Relationship Table
(1)
Notes: 1. Above tables are not specifications values, but rather the actual number of clock cycles. There are no gapless operations for
CAS latency 7 and 8.
2. Minimum clocks for gapless operation.
3. t
RC
(max) = t
VCVC
(max) = 50 µs. If t
RC
(max) or t
VCVC
(max) has been reached, a new “ACTIVE” command is necessary for
new access.
<
100 MHz
Burst Length RAS Latency CAS Latency t
RC
(min) t
VCVC
(min)
42
675
(2)
786
82
6119
(2)
71210
<75 MHz
Burst Length RAS Latency CAS Latency t
RC
(min) t
VCVC
(min)
42
564
(2)
675
82
5108
(2)
6119
<50 MHz
Burst Length RAS Latency CAS Latency t
RC
(min) t
VCVC
(min)
41
44
(2)
3/4
(2)
554
(2)
665
81
48
(2)
7/8
(2)
598
(2)
6109
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39

AT49LD3200-13TC

Mfr. #:
Buy AT49LD3200-13TC
Manufacturer:
Microchip Technology / Atmel
Description:
NOR Flash 32M bit
Lifecycle:
New from this manufacturer.
Delivery:
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