19
AT49LD3200(B)
1940B–FLASH–11/01
DQM Operation
Note: DQM makes data out high-Z after 2 CLKs, which should be masked by CKE “L”.
DQ
0
DQ
1
DQ
3
DQ
0
DQ
2
DQ
3
DQ
1
DQ
2
DQ
3
Masked by DQM
DQ
0
D1
DQ
1
DQ
3
DQ
0
DQ
7
DQ
2
DQ6 DQ7
DQ
1
DQ
7
DQ
6
DQ
5
CLK
CMD
DQM
Data
(
CL2
)
Data
(
CL3
)
Data
(
CL4
)
RD
CLK
CMD
DQM
CKE
RD
1
)
Read Mask
(
BL=4
)
2
)
DQM with Clock Sus
p
ended
(
BL=8
)
High-Z
High-Z
High-Z
DQ
5
DQ
4
DQ
3
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DQM to Data-out Mask = 2CLKs
High-Z
High-Z
High-Z
(
1
)
Data
(
CL2
)
Data
(
CL3
)
Data
(
CL4
)
20
AT49LD3200(B)
1940B–FLASH–11/01
Read Cycle I: Normal @RAS Latency = 2, CAS Latency = 5, Burst Length = 4
Note: When the burst length is 4 at 66 MHz, t
RC
is equal to 6 clock cycles.
0 1 2 3 4 5 6 7 8 9 10111213141516171819
tSS
tSH
CKE
CS
RAS
CAS
ADDR
Data
tCH
tCC
tCL
tRC
HIGH
tSH
t
SS
tSHZtSAC
tOH
DQa0 DQa1 DQa2 DQa3
CAbRAb
RAS
Latenc
y
MR
(
1
)
tRC=6 clocks at BL=4
Row Active Read Row Active Read
: Don't Care
t
SS
tSH
DQb0 DQb1 DQb2 DQb3
CAaRAa
CLK
21
AT49LD3200(B)
1940B–FLASH–11/01
Read Cycle II: Consecutive Column Access @RAS Latency = 2, CAS Latency = 5, Burst Length = 4
Note: When column access is initiated beyond t
VCVC
, at BL = 4, CA
a
access read is completed, CA
b
access read begins.
0 1 2 3 4 5 6 7 8 9 10111213141516171819
t
SS
t
SH
t
SS
t
SH
CKE
CS
RAS
CAS
ADDR
Data
t
CH
t
CC
t
CL
HIGH
t
SH
t
SS
CAaRAa
t
SHZ
t
SAC
t
OH
DQb1 DQb2 DQb3
CAb
DQb0
RAS
Latenc
y
t
VCVC
=4 clocks at BL=4
Burst Len
g
th=4 DQa1 DQa2 DQa3DQa0
MR
Row Active Read Read
: Don't Care
CLK

AT49LD3200-13TC

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
NOR Flash 32M bit
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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