22
AT49LD3200(B)
1940B–FLASH–11/01
Read Cycle III: Clock Suspend @RAS Latency = 2, CAS Latency = 5, Burst Length = 4
Notes: 1. From next clock after CKE goes low, clock suspension begins.
2. For clock suspension, data output state is held and maintained.
012345678910111213141516171819
t
SS
t
SH
CKE
CS
RAS
CAS
ADDR
Data
t
CH
t
CC
t
CL
t
SH
t
SS
CAaRAa
RAS
Latenc
y
t
VCVC
= 4 clocks at BL=4
(
2
)
Burst Len
g
th=4
DQa2
DQa3
DQa0
(
1
)
MR
Row Active Read
Clock Sus
p
end Resume
: Don't Care
DQa1
CLK
Internal
CLK
23
AT49LD3200(B)
1940B–FLASH–11/01
Read Interrupted by Precharge Command and Burst Read Stop Cycle @Burst Length = 8
Notes: 1. The Burst Stop command is valid at every page burst length. The data bus goes to high-Z after the CAS latency from the
Burst Stop command is issued.
2. The interval between Read command (column address presented) and Burst Stop command is 1 cycle (min).
0 1 2 3 4 5 6 7 8 9 10111213141516171819
HIGH
CL=3
ADDR
CAS
RAS
CS
CKE
CLK
MR
DQM
DQa0 DQa1 DQa2 DQa4 DQb0 DQb1 DQb2 DQb3 DQb4 DQb5
RAa CAa CAb
Row Active Prechar
g
eBurst Sto
p
Read Read
: Don't Care
(1)
CL=2
Data
DQa0 DQa1 DQa2 DQa4 DQb0 DQb1 DQb2 DQb3 DQb4 DQb5DQa3
DQa3
(1)(2)
(1)
(2)
(2)
24
AT49LD3200(B)
1940B–FLASH–11/01
Power-down and Clock Suspend Cycle: @RAS Latency = 2, CAS Latency = 5, Burst Length = 4
Notes: 1. From next clock after CKE goes low, clock suspend and power-down begins.
2. After power-down exit, NOP should be issued and new command can be issued after 1 clock.
3. Clock suspend is in active standby mode.
012345678910111213141516171819
CKE
CS
RAS
CAS
ADDR
Data
Read
CAaRAa
DQa1 DQa2DQa0
MR
DQa3
Row Active
(
Hi
g
h
)
CLK
(internal)
NOP
Power-down
Clock Sus
p
end
Entr
y
Entr
y
Power-down
Exit
Clock Sus
p
end
Exit
: Don't Care
t
SS
t
SH
(
2
)
(
1
)
t
SS
(
1
)
(
3
)
Clock Sus
p
endPower Down
Data Hi
g
h-Z State

AT49LD3200-13TC

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
NOR Flash 32M bit
Lifecycle:
New from this manufacturer.
Delivery:
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