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AT49LD3200-13TC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39
28
AT49LD3200(B)
1940B–FLASH–11/01
CAS Interrupt
Notes: 1. By “Interrupt”, it is meant to stop Burst Read by external command before the end of burst. By “CAS Interrupt”, to stop Burst
Read by CAS
access.
2. CAS
to CAS delay (=1 CLK).
Read Interrupt Operation by Issuing the Precharge of Burst Stop Command
Notes: 1. The data bus goes to high-Z after CAS latency from the Burst Stop (or precharge) command.
2. Valid output data will last up to CL-1 clock cycle from PRE command.
DQB1
DQB
2
RD
DQB
3
RD
A B
DQB
0
DQB
1
DQB
2
DQB
3
DQB
0
DQB1 DQB
2
DQB
3DQB0
(
2
)
Data
(
CL2
)
Data
(
CL3
)
Data
(
CL4
)
Read interru
p
ted b
y
Read
(
BL=4
)
(1)
CLK
CMD
ADD
RD PRE
DQ0
DQ0 DQ1
DQ0 DQ1
RD
STOP
DQ0 DQ1
DQ0 DQ1
DQ0 DQ1
DQ1
CLK
CMD
CLK
CMD
CASE I
)
Issued read Interru
p
t command durin
g
burst read o
p
eration
p
eriod.
RD PRE
DQ0
DQ0
DQ0
(
2
)
RD
STOP
DQ0
DQ0
DQ0
CLK
CMD
CLK
CMD
CASE II
)
Issued read Interru
p
t command between read command and data out.
(
2
)
(
1
)
(
1
)
Data
(
CL2
)
Data
(
CL3
)
Data
(
CL4
)
Data
(
CL2
)
Data
(
CL3
)
Data
(
CL4
)
Data
(
CL2
)
Data
(
CL3
)
Data
(
CL4
)
Data
(
CL2
)
Data
(
CL3
)
Data
(
CL4
)
29
AT49LD3200(B)
1940B–FLASH–11/01
Read Cycle Depending on t
RC
@RL = 2, CL = 6, BL = 4; 100 MHz
@RL = 2, CL = 5, BL = 4; 75 MHz
@RL = 1, CL = 4, BL = 4; 50 MHz
RDa
tRC(min)=7
ACT
tCC=10ns
CLK
CMD
CASE I )
CASE II )
CASE III )
RDbACT
RDb
DQb
1
DQb
2
DQb
0
DQb
1
DQb
2
DQb
3
DQb
0
DQa
1
DQa
2
DQa
0
DQa
3
DQa
1
DQa
2
DQa
0
DQa
3
High-Z
CASE I )
RDbACT
CASE II )
CASE III )
ACT
DQb
1
DQb
2
DQb
3
DQb
0
DQb
3
RDa
tRC(min)=6
ACT
tCC=15ns
RDbACT
RDb
DQb1 DQb2 DQb3DQb0
DQb1 DQb2 DQb3DQb0DQa1 DQa2DQa0 DQa3
DQa1 DQa2DQa0 DQa3
High-Z
CASE I )
RDbACT
CASE II )
CASE III )
ACT
DQb1 DQb2 DQb3DQb0
CLK
CMD
CASE I )
CASE II )
CASE III )
tRC(min)=4
ACT
tCC=20ns
ACT
DQb
1
DQb
2
DQb
3
DQb
0
DQb
1
DQb
2
DQb
3
DQb
0
DQa
1
DQa
2
DQa
0
DQa
3
DQa
1
DQa
2
DQa
0
DQa
3
CASE I )
ACT
CASE II)
CASE III)
ACT
DQb
1
DQb
2
DQb
3
DQb
0
CLK
CMD
CASE I )
CASE II )
CASE III )
RDa RDb
RDb
RDb
(Gapless Operation)
30
AT49LD3200(B)
1940B–FLASH–11/01
Read Cycle Depending on t
VCVC
@RL = 2, CL = 6, BL = 4; 100 MHz
@RL = 2, CL = 5, BL = 4; 75 MHz
@RL = 1, CL = 4, BL = 4; 50 MHz
tVCVC=5
ACT
CLK
CMD
CASE I )
CASE II )
CASE III )
RDa
DQb
1
DQb
2
DQb
3
DQb
0
CASE I)
CASE II)
CASE III)
DQb
1
DQb
2
DQb
3
DQb
0
DQb
1
DQb
2
DQb
3
DQb
0
DQa
0
DQa
1
DQa
0
RDb
RDb
RDb
DQa
2
DQa
3
DQa
1
(Gapless Operation)
DQa
3
DQa
2
tCC=10ns
tVCVC=4
ACT
DQb
1
DQb
2
DQb
3
DQb
0
CASE I)
CASE II)
CASE III)
CLK
CMD
CASE I )
CASE II )
CASE III )
DQb
1
DQb
2
DQb
3
DQb
0
DQb
1
DQb
2
DQb
3
DQb
0
DQa
0
DQa
1
DQa
0
RDa RDb
RDb
RDb
DQa
2
DQa
3
DQa
1
(Gapless Operation)
DQa
3
DQa
2
tCC=15ns
tVCVC=3
ACT
DQb
1
DQb
2
DQb
3
DQb
0
CASE I)
CASE II)
CASE III)
CLK
CMD
CASE I )
CASE II )
CASE III )
DQb
1
DQb
2
DQb
3
DQb
1
DQb
2
DQb
3
DQb
0
DQa
0
DQa
1
DQa
0
RDa RDb
RDb
RDb
DQa
3
DQa
2
(Gapless Operation)
: Invalid Data
DQa
2
DQa
1
tCC=20ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39

AT49LD3200-13TC

Mfr. #:
Buy AT49LD3200-13TC
Manufacturer:
Microchip Technology / Atmel
Description:
NOR Flash 32M bit
Lifecycle:
New from this manufacturer.
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