16
AT49LD3200(B)
1940B–FLASH–11/01
Boot Block Lockout command, which is a synchronous five-bus cycle operation, must be
performed (refer to Command Definitions table and Program Cycle Waveforms).
A software method is available to determine if programming or erasing of the boot block
is locked out. Issue Boot Block Lockout Verify command and observe DQ
0
~ DQ
7
. If the
data show 00H/02H, the boot block can be programmed or erased; if the data show
01H/03H, the lockout feature has been enabled and the boot block cannot be pro-
grammed or erased. The Boot Block Lockout Verify Exit command should be used to
return to standard operation (refer to Command Definition table and Boot Block Lockout
Verify Waveforms).
The user can override the boot block lockout by taking the MR
pin to 12 volts after the
boot block is activated. When the MR
pin is brought back to TTL levels, the boot block
lockout feature is again active.
17
AT49LD3200(B)
1940B–FLASH–11/01
Notes: 1. The DATA FORMAT in each bus cycle is as follows: DQ31 - DQ8 (Don’t Care); DQ7 - DQ0 (Hex).
2. SA = Sector Addresses: Any word/double word address within a sector can be used to designate the sector address.
See Sector Address Mapping table below.
3. Allow minimum 200 ns after Boot Block Lockout Verify command and before Read.
4. Allow minimum 10 µs after Boot Block Lockout Verify Exit command for the device to return to standard operation.
Command Definition in Hex
(1)
Command
Sequence
Bus
Cycles
1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle
RA CA Data RA CA Data RA CA Data RA CA Data RA CA Data RA CA Data
Word/
Double
Word
Program
4 AA55AA552A55AA55A0RACAD
IN
Sector
Erase
6 AA55AA552A55AA5580AA55AA552A55SA
(2)
X30
Continuity
Test Mode
Entry
5 AA55AA552A55AA5580AA55AAAA5570
Boot Block
Lockout
5 AA55AA552A55AA5580AA55AAAA5540
Boot Block
Lockout
Verify
5 AA55AA552A55AA5580AA55AAAA5590
Boot Block
Lockout
Verify Exit
5 AA55AA552A55AA5580AA55AAAA55F0
Sector Address Mapping
Sector Size (Word/Double Word)
x16
Address Range
x32
Address Range
CA
7-0
RA
12-0
CA
6-0
RA
12-0
SA0 256K/128K X
00XX
03XX
X
00XX
03XX
SA1 256K/128K X
04XX
07XX
X
04XX
07XX
SA2 256K/128K X
08XX
0BXX
X
08XX
0BXX
SA3 256K/128K X
0CXX
0FXX
X
0CXX
0FXX
SA4 256K/128K X
10XX
13XX
X
10XX
13XX
SA5 256K/128K X
14XX
17XX
X
14XX
17XX
SA6 256K/128K X
18XX
1BXX
X
18XX
1BXX
SA7 256K/128K X
1CXX
1FXX
X
1CXX
1FXX
18
AT49LD3200(B)
1940B–FLASH–11/01
Basic Feature and Function Descriptions
MRS
Clock Suspend
Clock Suspend Exit and Power-down Exit
Note: After Mode Register Set command is completed, no new commands can be issued for 3 clock cycles, and MR or CS should be
fixed “H” within a minimum of 3 clock cycles.
Mode Re
g
ister Set
CLK
CMD MRS ACT
(
1
)
3CLK
D0
Internal
CLK
Clock Sus
p
ended Durin
g
Burst Read
(
BL=4
)
Masked by CKE
DQ
0 DQ1 DQ2 DQ3
Sus
p
ended Dout
CLK
CMD RD
CKE
Data
: This command cannot be activated.
Internal
CLK
CKE
Internal
CLK
1
)
Clock Sus
p
end Exit
CLK
CKE
CMD
RD
2
)
Power Down
CLK
CMD
NOP ACT
tSStSS

AT49LD3200-13TC

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
NOR Flash 32M bit
Lifecycle:
New from this manufacturer.
Delivery:
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