PCA8546 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 13 November 2013 13 of 63
NXP Semiconductors
PCA8546
4 x 44 automotive LCD driver
[1] When RESET is active, the pin OSCCLK is in 3-state.
[2] In this state, an external clock may be applied, but it is not a requirement.
[3] 9.6 kHz is the nominal frequency with q = 24, see Table 14
.
External clock: In applications where an external clock must be applied to the PCA8546,
bit OSC (see Table 10
) has to be set logic 1. In this case pin OSCCLK becomes an input.
The OSCCLK signal must switch between the V
SS
and the V
DD
voltage supplied to the
chip.
The EFR bit determines the external clock frequency (230 kHz or 9.6 kHz). The clock
frequency (f
clk(ext)
) in turn determines the LCD frame frequency, see Table 14.
Remark: If an external clock is used, then this clock signal must always be supplied to the
device when the display is on. Removing the clock may freeze the LCD in a DC state
which damages the LCD material.
8.1.4.2 Timing and frame frequency
The timing of the PCA8546 organizes the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs. The
timing also generates the LCD frame frequency which it derives as an integer division of
the clock frequency (see Table 14
). The frame frequency is a fixed division of the internal
clock or of the frequency applied to pin OSCCLK when an external clock is used.
[1] Other values of the frame frequency prescaler see Table 17.
When the internal clock is used, or an external clock with EFR = 1, the LCD frame
frequency can be programmed by software in steps of approximately 10 Hz in the range of
60 Hz to 300 Hz (see Table 17
). Furthermore the internal oscillator is factory calibrated,
see Table 32 on page 42
.
8.1.5 Command: set-bias-mode
The set-bias-mode command allows setting the bias level.
Table 13. OSCCLK pin state depending on configuration
PD OSC COE EFR OSCCLK pin
[1]
power-down n.a. off n.a. 3-state
[2]
power-downn.a.on n.a.V
DD
power-up internal oscillator off n.a. 3-state
on n.a. 9.6 kHz output
[3]
external oscillator n.a. 9.6 kHz 9.6 kHz input
230 kHz 230 kHz input
Table 14. LCD frame frequencies
Frame frequency Typical external
frequency (Hz)
Nominal frame
frequency (Hz)
EFR bit Value of q
[1]
9600 200 0 -
230000 200 1 24
f
fr LCD
f
clk ext
48
-----------------
=
f
fr LCD
f
clk ext
48 q
-----------------
=
