PCA8546 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 13 November 2013 29 of 63
NXP Semiconductors
PCA8546
4 x 44 automotive LCD driver
9. Bus interfaces
9.1 Control byte and register selection
After initiating the communication over the bus and sending the slave address (I
2
C-bus,
see Section 9.2
) or subaddress (SPI-bus, see Section 9.3), a control byte follows. The
purpose of this byte is to indicate both, the content for the following data bytes (RAM, or
command) and to indicate that more control bytes will follow.
Typical sequences could be:
• Slave address/subaddress - control byte - command byte - command byte - command
byte - end
• Slave address/subaddress - control byte - RAM byte - RAM byte - RAM byte - end
• Slave address/subaddress - control byte - command byte - control byte - RAM byte -
end
In this way, it is possible to send a mixture of RAM and command data in one access or
alternatively, to send just one type of data in one access.
9.2 I
2
C-bus interface
The I
2
C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
Table 23. Control byte description
Bit Symbol Value Description
7CO continue bit
0 last control byte
1 control bytes continue
6 to 5 RS[1:0] register selection
00 command register
01 RAM data
10, 11 unused
4 to 0 - - unused
Fig 19. Control byte format
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&2
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