PCA8546 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 13 November 2013 43 of 63
NXP Semiconductors
PCA8546
4 x 44 automotive LCD driver
[1] The minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either the SDA or SCL
is held LOW for a minimum of 25 ms. The bus time-out feature must be disabled for DC operation.
[2] t
VD;ACK
= time for acknowledgement signal from SCL LOW to SDA output LOW.
[3] t
VD;DAT
= minimum time for valid SDA output following SCL LOW.
[4] Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.
Fig 36. RESET timing
DDD
5(6(7
W
5(6(7/
9
''
Table 33. Timing characteristics: I
2
C-bus
V
DD
= 1.8 V to 5.5 V; V
SS
= 0 V; T
amb
=
40
C to +95
C; unless otherwise specified. All timing values are valid within the
operating supply voltage and temperature range and referenced to V
IL
and V
IH
with an input voltage swing of V
SS
to V
DD
.
Timing waveforms see Figure 37
.
Symbol Parameter Conditions Min Typ Max Unit
Pin SCL
f
SCL
SCL clock frequency
[1]
--400kHz
t
LOW
LOW period of the SCL clock 1.3 - - s
t
HIGH
HIGH period of the SCL clock 0.6 - - s
Pin SDA
t
SU;DAT
data set-up time 100 - - ns
t
HD;DAT
data hold time 0 - - ns
Pins SCL and SDA
t
BUF
bus free time between a STOP
and START condition
1.3 - - s
t
SU;STO
set-up time for STOP condition 0.6 - - s
t
HD;STA
hold time (repeated) START
condition
0.6 - - s
t
SU;STA
set-up time for a repeated START
condition
0.6 - - s
t
r
rise time of both SDA and SCL
signals
f
SCL
= 400 kHz - - 0.3 s
f
SCL
= 100 kHz - - 1.0 s
t
f
fall time of both SDA and SCL
signals
--0.3s
t
VD;ACK
data valid acknowledge time
[2]
0.6 - - s
t
VD;DAT
data valid time
[3]
0.6 - - s
C
b
capacitive load for each bus line - - 400 pF
t
SP
pulse width of spikes that must be
suppressed by the input filter
[4]
--50ns
