W77IE58
Publication Release Date: October 20, 2005
- 25 - Revision A5
HC5: Hardware Clear
INT5 flag. Setting this bit allows the flag of external interrupt 5 to be
automatically cleared by hardware while entering the interrupt service routine.
HC4: Hardware Clear INT4 flag. Setting this bit allows the flag of external interrupt 4 to be
automatically cleared by hardware while entering the interrupt service routine.
HC3: Hardware Clear
INT3 flag. Setting this bit allows the flag of external interrupt 3 to be
automatically cleared by hardware while entering the interrupt service routine.
HC3: Hardware Clear INT2 flag. Setting this bit allows the flag of external interrupt 3 to be
automatically cleared by hardware while entering the interrupt service routine.
T2CR: Timer 2 Capture Reset. In the Timer 2 Capture Mode this bit enables/disables hardware
automatically reset Timer 2 while the value in TL2 and TH2 have been transferred into the
capture register.
T2OE: Timer 2 Output Enable. This bit enables/disables the Timer 2 clock out function.
DCEN: Down Count Enable: This bit, in conjunction with the T2EX pin, controls the direction that
timer 2 counts in 16-bit auto-reload mode.
Timer 2 Capture LSB
Bit: 7 6 5 4 3 2 1 0
RCAP2L.7 RCAP2L.6 RCAP2L.5 RCAP2L.4 RCAP2L.3 RCAP2L.2 RCAP2L.1 RCAP2L.0
Mnemonic: RCAP2L Address: CAh
RCAP2L: This register is used to capture the TL2 value when a timer 2 is configured in capture mode.
RCAP2L is also used as the LSB of a 16-bit reload value when timer 2 is configured in auto-
reload mode.
Timer 2 Capture MSB
Bit: 7 6 5 4 3 2 1 0
RCAP2H.7 RCAP2H.6 RCAP2H.5 RCAP2H.4 RCAP2H.3 RCAP2H.2 RCAP2H.1 RCAP2H.0
Mnemonic: RCAP2H Address: CBh
RCAP2H: This register is used to capture the TH2 value when a timer 2 is configured in capture
mode.
RCAP2H is also used as the MSB of a 16-bit reload value when timer 2 is configured in
auto-reload mode.
Timer 2 LSB
Bit: 7 6 5 4 3 2 1 0
TL2.7 TL2.6 TL2.5 TL2.4 TL2.3 TL2.2 TL2.1 TL2.0
Mnemonic: TL2 Address: CCh
TL2: Timer 2 LSB
W77IE58
- 26 -
Timer2 MSB
Bit: 7 6 5 4 3 2 1 0
TH2.7 TH2.6 TH2.5 TH2.4 TH2.3 TH2.2 TH2.1 TH2.0
Mnemonic: TH2 Address: CDh
TH2: Timer 2 MSB
Program Status Word
Bit: 7 6 5 4 3 2 1 0
CY AC F0 RS1 RS0 OV F1 P
Mnemonic: PSW Address: D0h
CY: Carry flag: Set for an arithmetic operation which results in a carry being generated from the
ALU. It is also used as the accumulator for the bit operations.
AC: Auxiliary carry: Set when the previous operation resulted in a carry from the high order nibble.
F0: User flag 0: General purpose flag that can be set or cleared by the user.
RS.1-0: Register bank select bits:
RS1 RS0 Register bank Address
0 0 0 00-07h
0 1 1 08-0Fh
1 0 2 10-17h
1 1 3 18-1Fh
OV: Overflow flag: Set when a carry was generated from the seventh bit but not from the 8th bit as
a result of the previous operation, or vice-versa.
F1: User Flag 1: General purpose flag that can be set or cleared by the user by software.
P: Parity flag: Set/cleared by hardware to indicate odd/even number of 1's in the accumulator.
Watchdog Control
Bit: 7 6 5 4 3 2 1 0
SMOD_1 POR - - WDIF WTRF EWT RWT
Mnemonic: WDCON Address: D8h
SMOD_1:This bit doubles the Serial Port 1 baud rate in mode 1, 2, and 3 when set to 1.
POR: Power-on reset flag. Hardware will set this flag on a power up condition. This flag can be read
or written by software. A write by software is the only way to clear this bit once it is set.
WDIF: Watchdog Timer Interrupt Flag. If the watchdog interrupt is enabled, hardware will set this bit
to indicate that the watchdog interrupt has occurred. If the interrupt is not enabled, then this bit
indicates that the time-out period has elapsed. This bit must be cleared by software.
W77IE58
Publication Release Date: October 20, 2005
- 27 - Revision A5
WTRF: Watchdog Timer Reset Flag. Hardware will set this bit when the watchdog timer causes a
reset. Software can read it but must clear it manually. A power-fail reset will also clear the bit.
This bit helps software in determining the cause of a reset. If EWT = 0, the watchdog timer
will have no affect on this bit.
EWT: Enable Watchdog timer Reset. Setting this bit will enable the Watchdog timer Reset function.
RWT: Reset Watchdog Timer. This bit helps in putting the watchdog timer into a know state. It also
helps in resetting the watchdog timer before a time-out occurs. Failing to set the EWT before
time-out will cause an interrupt, if EWDI (EIE.4) is set, and 512 clocks after that a watchdog
timer reset will be generated if EWT is set. This bit is self-clearing by hardware.
The WDCON SFR is set to a 0x0x0xx0b on an external reset. WTRF is set to a 1 on a Watchdog timer
reset, but to a 0 on power on/down resets. WTRF is not altered by an external reset. POR is set to 1
by a power-on reset. EWT is set to 0 on a Power-on reset and unaffected by other resets.
All the bits in this SFR have unrestricted read access. POR, EWT, WDIF and RWT require Timed
Access procedure to write. The remaining bits have unrestricted write accesses.
Accumulator
Bit: 7 6 5 4 3 2 1 0
ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0
Mnemonic: ACC Address: E0h
ACC.7-0: The A (or ACC) register is the standard 8052 accumulator.
Extended Interrupt Enable
Bit: 7 6 5 4 3 2 1 0
- - - EWDI EX5 EX4 EX3 EX2
Mnemonic: EIE Address: E8h
EIE.7-5: Reserved bits, will read high.
EWDI: Enable Watchdog timer interrupt.
EX5: External Interrupt 5 Enable.
EX4: External Interrupt 4 Enable.
EX3: External Interrupt 3 Enable.
EX2: External Interrupt 2 Enable.

W77I058A25PL

Mfr. #:
Manufacturer:
Description:
IC MCU 8BIT 32KB FLASH 44PLCC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet