W77I058A25PL Datasheet W77I058A25DL, W77I058A25PL | P61-P63

W77IE58

Publication Release Date: October 20, 2005

- 61 - Revision A5

Serial Port

Serial port in the W77IE58 is a full duplex port. The W77IE58 provides the user with additional

features such as the Frame Error Detection and the Automatic Address Recognition. The serial ports

are capable of synchronous as well as asynchronous communication. In Synchronous mode the

W77IE58 generates the clock and operates in a half duplex mode. In the asynchronous mode, full

duplex operation is available. This means that it can simultaneously transmit and receive data. The

transmit register and the receive buffer are both addressed as SBUF Special Function Register.

However any write to SBUF will be to the transmit register, while a read from SBUF will be from the

receive buffer register. The serial port can operate in four different modes as described below.

MODE 0

This mode provides synchronous communication with external devices. In this mode serial data is

transmitted and received on the RXD line. TXD is used to transmit the shift clock. The TxD clock is

provided by the W77IE58 whether the device is transmitting or receiving. This mode is therefore a half

duplex mode of serial communication. In this mode, 8 bits are transmitted or received per frame. The

LSB is transmitted/received first. The baud rate is fixed at 1/12 or 1/4 of the oscillator frequency. This

baud rate is determined by the SM2 bit (SCON.5). When this bit is set to 0, then the serial port runs at

1/12 of the clock. When set to 1, the serial port runs at 1/4 of the clock. This additional facility of

programmable baud rate in mode 0 is the only difference between the standard 8051 and the

W77IE58.

The functional block diagram is shown below. Data enters and leaves the Serial port on the RxD line.

The TxD line is used to output the shift clock. The shift clock is used to shift data into and out of the

W77IE58 and the device at the other end of the line. Any instruction that causes a write to SBUF will

start the transmission. The shift clock will be activated and data will be shifted out on the RxD pin till all

8 bits are transmitted. If SM2 = 1, then the data on RxD will appear 1 clock period before the falling

edge of shift clock on TxD. The clock on TxD then remains low for 2 clock periods, and then goes high

again. If SM2 = 0, the data on RxD will appear 3 clock periods before the falling edge of shift clock on

TxD. The clock on TxD then remains low for 6 clock periods, and then goes high again. This ensures

that at the receiving end the data on RxD line can either be clocked on the rising edge of the shift

clock on TxD or latched when the TxD clock is low.

W77IE58

- 62 -

SBUF

Transmit Shift Register

Receive Shift Register

SHIFT

PAROUT

Internal

Data Bus

Internal

Data Bus

RXD

P3.0 Alternate

Output Function

TXD

P3.1 Alternate

Output function

RXD

P3.0 Alternate

Iutput function

Serial Port Interrupt

Write to

SBUF

START

SOUT

REN

PARIN

LOAD

CLOCK

Read SBUF

SBUF

TX CLOCK

SERIAL

CONTROLLE

SHIFT

CLOCK

LOAD SBUF

START

RX SHIFT

CLOCK

SIN

412

SM2

Clock Source

Mode input

div. by 4 osc/1

div. by 64 osc/16

div. by 1024 osc/256

Figure 20. Serial Port Mode 0

The TI flag is set high in C1 following the end of transmission of the last bit. The serial port will receive

data when REN is 1 and RI is zero. The shift clock (TxD) will be activated and the serial port will latch

data on the rising edge of shift clock. The external device should therefore present data on the falling

edge on the shift clock. This process continues till all the 8 bits have been received. The RI flag is set

in C1 following the last rising edge of the shift clock on TxD. This will stop reception, till the RI is

cleared by software.

MODE 1

In Mode 1, the full duplex asynchronous mode is used. Serial communication frames are made up of

10 bits transmitted on TXD and received on RXD. The 10 bits consist of a start bit (0), 8 data bits (LSB

first), and a stop bit (1). On receive, the stop bit goes into RB8 in the SFR SCON. The baud rate in this

mode is variable. The serial baud can be programmed to be 1/16 or 1/32 of the Timer 1 overflow.

Since the Timer 1 can be set to different reload values, a wide variation in baud rates is possible.

Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin at C1 following

the first roll-over of divide by 16 counter. The next bit is placed on TxD pin at C1 following the next

rollover of the divide by 16 counter. Thus the transmission is synchronized to the divide by 16 counter

and not directly to the write to SBUF signal. After all 8 bits of data are transmitted, the stop bit is

transmitted. The TI flag is set in the C1 state after the stop bit has been put out on TxD pin. This will

be at the 10th rollover of the divide by 16 counter after a write to SBUF.

Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data,

with the detection of a falling edge on the RxD pin. The 1-to-0 detector continuously monitors the RxD

line, sampling it at the rate of 16 times the selected baud rate. When a falling edge is detected, the

divide by 16 counter is immediately reset. This helps to align the bit boundaries with the rollovers of

the divide by 16 counter.

W77IE58

Publication Release Date: October 20, 2005

- 63 - Revision A5

The 16 states of the counter effectively divide the bit time into 16 slices. The bit detection is done on a

best of three basis. The bit detector samples the RxD pin, at the 8th, 9th and 10th counter states. By

using a majority 2 of 3 voting system, the bit value is selected. This is done to improve the noise

rejection feature of the serial port. If the first bit detected after the falling edge of RxD pin is not 0, then

this indicates an invalid start bit, and the reception is immediately aborted. The serial port again looks

for a falling edge in the RxD line. If a valid start bit is detected, then the rest of the bits are also

detected and shifted into the SBUF.

After shifting in 8 data bits, there is one more shift to do, after which the SBUF and RB8 are loaded

and RI is set. However certain conditions must be met before the loading and setting of RI can be

done.

1. RI must be 0 and

2. Either SM2 = 0, or the received stop bit = 1.

If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set.

Otherwise the received frame may be lost. After the middle of the stop bit, the receiver goes back to

looking for a 1-to-0 transition on the RxD pin.

SBUF

RB8

Transmit Shift Register

Receive Shift

TX SHIFT

PAROUT

Internal

Data Bus

Internal

Data

Bus

TXD

RXD

Serial Port

Interrupt

SMOD=

(SMOD_1)

TCLK

RCLK

SAMPLE

Write to

SBUF

TX START

SOUT

0 1

PARIN

STOP

START

LOAD

CLOCK

Read

SBUF

Timer 2 Overflow

(for Serial Port 0 only)

Timer 1

Overflow

TX CLOCK

SERIAL

CONTROLLER

RX CLOCK

LOAD

SBUF

START

RX SHIFT

1-TO-0

DETECTOR

BIT

DETECTOR

CLOCK

SIN

Figure 21. Serial Port Mode 1

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P60 P61-P63 P64-P66 P67-P69 P70-P72 P73-P75 P76-P78 P79-P81 P82-P82

W77I058A25PL

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W77I058A25PL

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