W77IE58
Publication Release Date: October 20, 2005
- 45 - Revision A5
Economy Mode
The power consumption of microcontroller relates to operating frequency. The W77IE58 offers a
Economy mode to reduce the internal clock rate dynamically without external components. By default,
one machine cycle needs 4 clocks. In Economy mode, software can select 4, 64 or 1024 clocks per
machine cycle. It keeps the CPU operating at a acceptable speed but eliminates the power
consumption. In the Idle mode, the clock of the core logic is stopped, but all clocked peripherals such
as watchdog timer are still running at a rate of clock/4. In the Economy mode, all clocked peripherals
run at the same reduced clocks rate as in core logic. So the Economy mode may provide a lower
power consumption than idle mode.
Software invokes the Economy mode by setting the appropriate bits in the SFRs. Setting the bits
CD0(PMR.6), CD1(PMR.7) decides the instruction cycle rate as below:
CD1 CD0 Clocks/Machine cycle
0 0 Reserved
0 1 4 (default)
1 0 64
1 1 1024
The selection of instruction rate is going to take effect after a delay of one instruction cycle. Switching
to divide by 64 or 1024 mode must first go from divide by 4 mode. This means software can not switch
directly between clock/64 and clock/1024 mode. The CPU has to return clock/4 mode first, then go to
clock/64 or clock/1024 mode.
The W77IE58 allows the user to use internal RC oscillator instead of external crystal. Setting the
XT/
RG bit (EXIF.3) selects the crystal or RC oscillator as the clock source. When invoking RC
oscillator in Economy mode, software may set the XTOFF bit to turn off the crystal amplifier for saving
power. The CPU would run at the clock rate of approximately 2−4 MHz divided by 4, 64 or 1024. The
RC oscillator is not precise so that can not be invoked to the operation which needs the accurate time-
base such as serial communication. The RGMD(EXIF.2) indicates current clock source. When
switching the clock source, CPU needs one instruction cycle delay to take effect new setting. If crystal
amplifier is disabled and RC oscillator is present clock source, software must first clear the XTOFF bit
to turn on crystal amplifier before switch to crystal operation. Hardware will set the XTUP bit
(STATUS.4) once the crystal is warm-up and ready for use. It is unable to set XT/
RG bit to 1 if XTUP
= 0.
In Economy mode, the serial port can not receive/transmit data correctly because the baud rate is
changed. In some systems, the external interrupts may require the fastest process such that the
reducing of operating speed is restricted. In order to solve these dilemmas, the W77IE58 offers a
switchback feature which allows the CPU back to clock/4 mode immediately when triggered by serial
operation or external interrupts. The switchback feature is enabled by setting the SWB bit (PMR.5). A
serial port reception/transmission or qualified external interrupt which is enabled and acknowledged
without block conditions will cause CPU to return to divide by 4 mode. For the serial port reception, a
switchback is generated by a falling edge associated with start bit if the serial port reception is
enabled. When a serial port transmission, an instruction which writes a byte of data to serial port
buffer will cause a switchback to ensure the correct transmission. The switchback feature is
unaffected by serial port interrupt flags. After a switchback is generated, the software can manually
return the CPU to Economy mode. Note that the modification of clock control bits CD0 and CD1 will be
ignored during serial port transmit/receive when switchback is enabled. The Watchdog timer reset,
power-on/fail reset or external reset will force the CPU to return to divide by 4 mode.
