W77IE58
Publication Release Date: October 20, 2005
- 67 - Revision A5
Slave 2:
SADDR 1010 0111
SADEN 1111 1001
Given 1010 0xx1
The Given address for slave 1 and 2 differ in the LSB. For slave 1, it is a don't care, while for slave 2 it
is 1. Thus to communicate only with slave 1, the master must send an address with LSB = 0 (1010
0000). Similarly the bit 1 position is 0 for slave 1 and don't care for slave 2. Hence to communicate
only with slave 2 the master has to transmit an address with bit 1 = 1 (1010 0011). If the master
wishes to communicate with both slaves simultaneously, then the address must have bit 0 = 1 and bit
1 = 0. The bit 3 position is don't care for both the slaves. This allows two different addresses to select
both slaves (1010 0001 and 1010 0101).
The master can communicate with all the slaves simultaneously with the Broadcast Address. This
address is formed from the logical ORing of the SADDR and SADEN SFRs. The zeros in the result
are defined as don't cares In most cases the Broadcast Address is FFh. In the previous case, the
Broadcast Address is (1111111X) for slave 1 and (11111111) for slave 2.
The SADDR and SADEN SFRs are located at address A9h and B9h respectively. On reset, these two
SFRs are initialized to 00h. This results in Given Address and Broadcast Address being set as XXXX
XXXX(i.e. all bits don't care). This effectively removes the multiprocessor communications feature,
since any selectivity is disabled.
9. TIMED ACCESS PROTECTION
The W77IE58 has several new features, like the Watchdog timer, on-chip ROM size adjustment, wait
state control signal and Power on/fail reset flag, which are crucial to proper operation of the system. If
left unprotected, errant code may write to the Watchdog control bits resulting in incorrect operation
and loss of control. In order to prevent this, the W77IE58 has a protection scheme which controls the
write access to critical bits. This protection scheme is done using a timed access.
In this method, the bits which are to be protected have a timed write enable window. A write is
successful only if this window is active, otherwise the write will be discarded. This write enable window
is open for 3 machine cycles if certain conditions are met. After 3 machine cycles, this window
automatically closes. The window is opened by writing AAh and immediately 55h to the Timed
Access(TA) SFR. This SFR is located at address C7h. The suggested code for opening the timed
access window is
TA REG 0C7h ; define new register TA, located at 0C7h
MOV TA, #0AAh
MOV TA, #055h
When the software writes AAh to the TA SFR, a counter is started. This counter waits for 3 machine
cycles looking for a write of 55h to TA. If the second write (55h) occurs within 3 machine cycles of the
first write (AAh), then the timed access window is opened. It remains open for 3 machine cycles,
during which the user may write to the protected bits. Once the window closes the procedure must be
repeated to access the other protected bits.
Examples of Timed Assessing are shown below.
