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W77I058A25PL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P78P79-P81P82-P82
W77IE58
- 76 -
Explanation of Logic Symbols
In order to maintain compatibility with the original 8051 family, this device specifies the same
parameter for each device, using the same symbols. The explanation of the symbols is as follows.
t Time A Address
C Clock D Input Data
H Logic level high L Logic level low
I Instruction P
PSEN
Q Output Data R
RD signal
V Valid W
WR signal
X No longer a valid state Z Tri-state
W77IE58
Publication Release Date: October 20, 2005
- 77 - Revision A5
13. TIMING WAVEFORMS
Program Memory Read Cycle
t
LLAX1
t
PXIZ
t
PLAZ
t
LLPL
t
PXIX
t
PLIV
t
AVIV2
t
AVIV1
t
PLPH
t
AVLL
ADDRESS A8-A15ADDRESS A8-A15
ADDRESS
A0-A7
INSTRUCTION
IN
ADDRESS
A0-A7
PORT 2
PORT 0
PSEN
ALE
t
LLIV
t
LHLL
Data Memory Read Cycle
t
AVLL
t
AVWL1
t
LLAX1
t
WHLH
t
RLDV
t
RLRH
t
RLAZ
t
RHDZ
t
RHDX
t
AVDV2
t
AVDV1
t
LLWL
ADDRESS A8-A15
ADDRESS
A0-A7
INSTRUCTION
IN
DATA
IN
ADDRESS
A0-A7
PORT 2
PORT 0
PSEN
RD
ALE
t
LLDV
W77IE58
- 78 -
Timing Waveforms, continued
Data Memory Write Cycle
t
AVLL
t
AVWL1
t
LLAX2
t
WHLH
t
WLWH
t
QVWX
t
WHQX
t
AVDV2
t
LLWL
ADDRESS A8-A15
ADDRESS
A0-A7
INSTRUCTION
IN
DATA OUT
ADDRESS
A0-A7
PORT 2
PORT 0
PSEN
WR
ALE
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P78P79-P81P82-P82

W77I058A25PL

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IC MCU 8BIT 32KB FLASH 44PLCC
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