W77IE58
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8.1.4 Auto-reload Mode, Counting Up
The auto-reload mode as an up counter is enabled by clearing the
CP RL/2 bit in the T2CON
register. RCLK and TCLK bits must be cleared and clearing the DCEN bit in T2MOD register. In this
mode, Timer/Counter 2 is a 16 bit up counter. When the counter rolls over from FFFFh, a reload is
generated that causes the contents of the RCAP2L and RCAP2H registers to be reloaded into the TL2
and TH2 registers. The reload action also sets the TF2 bit. If the EXEN2 bit is set, then a negative
transition of T2EX pin will also cause a reload. This action also sets the EXF2 bit in T2CON.
1/4
1/12
T2M = CKCON.5
C/T2 = T2CON.1
T2CON.7
T2 = P1.0
T2CON.6
TR2 =
T2CON.2
T2EX = P1.1
EXEN2 = T2CON.3
EXF2
Timer 2
Interrupt
TF2
TH2TL2
RCAP2HRCAP2L
1
0
0
1
Clock Source
Mode input
div. by 4 osc/1
div. by 64 osc/16
div. by 1024 osc/256
DCEN = 0
Figure 15. 16-Bit Auto-reload Mode, Counting Up
8.1.5 Auto-reload Mode, Counting Up/Down
Timer/Counter 2 will be in auto-reload mode as an up/down counter if
CP RL/2 bit in T2CON is
cleared. RCLK and TCLK bits must be cleared and the DCEN bit in T2MOD is set. In this mode,
Timer/Counter 2 is an up/down counter whose direction is controlled by the T2EX pin. A 1 on this pin
cause the counter to count up. An overflow while counting up will cause the counter to be reloaded
with the contents of the capture registers. The next down count following the case where the contents
of Timer/Counter equal the capture registers will load an FFFFh into Timer/Counter 2. In either event a
reload will set the TF2 bit. A reload will also toggle the EXF2 bit. However, the EXF2 bit can not
generate an interrupt while in this mode.
