W77IE58
Publication Release Date: October 20, 2005
- 73 - Revision A5
D.C. Characteristics, continued
SPECIFICATION
PARAMETER SYM.
MIN. MAX. UNIT
TEST CONDITIONS
Input High Voltage RST 3.5 VDD +0.2 V VDD = 5.5V
V
IH2
2.2 V
DD +0.2 V VDD = 3.0V
Input High Voltage 3.5 VDD +0.2 V VDD = 5.5V
XTAL1
[*3]
V
IH3
2.4 V
DD +0.2 V VDD = 3.0V
Output Low Voltage - 0.45 V VDD = 4.5V, IOL = +4 mA
P1, P2, P3, P4
V
OL1
- 0.40 V V
DD = 3V, IOL = +4 mA
Output Low Voltage - 0.45 V VDD = 4.5V, IOL = +10 mA
P0, ALE, PSEN
[*2]
V
OL2
- 0.40 V V
DD = 3V, IOL = +6 mA
Output High Voltage
P1, P2, P3, P4
V
OH1 2.4 - V
V
DD = 4.5V, IOH = -120 μA
V
DD = 3.0V, IOH = -45 μA
Output High Voltage
P0, ALE,
PSEN
[*2]
V
OH2 2.4 - V
V
DD = 4.5V, IOH = -8 mA
V
DD = 3.0V, IOH = -3 mA
Notes:
*1. RST pin is a Schmitt trigger input.
*2. P0, ALE and
PSEN
are tested in the external access mode.
*3. XTAL1 is a CMOS input.
*4. Pins of P1, P2, P3 can source a transition current when they are being externally driven from 1 to 0. The transition
current reaches its maximum value when VIN approximates to 2V.
12.3 A.C. Characteristics
t
CLCL
t
CLCX
t
CHCX
t
CLCH
t
CHCL
Note: Duty cycle is 50%.
External Clock Characteristics
PARAMETER SYMBOL MIN. TYP. MAX. UNITS NOTES
Clock High Time t
CHCX
20 - - nS
Clock Low Time t
CLCX
20 - - nS
Clock Rise Time t
CLCH
- - 10 nS
Clock Fall Time t
CHCL
- - 10 nS
