W77IE58
- 70 -
OPERATIONS
P3.0
(A9
CTRL)
P3.1
(A13
CTRL)
P3.2
(A14
CTRL)
P3.3
(OE
CTRL)
P3.6
(
CE)
P3.7
( OE )
E
A
(VPP)
P2, P1
(A15..A0)
P0
(D7..D0)
NOTE
Read 0 0 0 0 0 0 1 Address Data Out
Output Disable 0 0 0 0 0 1 1 X Hi-Z
Program 0 0 0 0 0 1 VCP Address Data In
Program Verify 0 0 0 0 1 0 VCP Address Data Out @3
Erase 1 0 0 0 0 1 VEP
A0:0,
others: X
Data In
0FFH
@4
Erase Verify 1 0 0 0 1 0 VEP Address Data Out @5
Program/Erase
Inhibit
X 0 0 0 1 1
VCP/
VEP
X X
Notes:
1. All these operations happen in RST = V
IH, ALE = VIL and PSEN = VIH.
2. V
CP = 12.5V, VEP = 14.5V, VIH = VDD, VIL = VSS.
3. The program verify operation follows behind the program operation.
4. This erase operation will erase all the on-chip ROM cells and the Security bits.
5. The erase verify operation follows behind the erase operation.
P1
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
X'tal1
X'tal2
P0
EA/Vpp
ALE
RST
PSEN
P2
Vss
Vcc
A0-A7
V
CP
V
IL
V
IH
V
IL
V
IL
V
IL
V
IL
V
IL
A8-A15
PGM DATA
V
IH
V
IH
+5V
Programming Configuration
P1
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
X'tal1
X'tal2
P0
EA/Vpp
ALE
RST
PSEN
P2
Vss
Vcc
A0-A7
V
CP
V
IL
V
IH
V
IL
V
IL
V
IL
V
IL
V
IL
A8-A15
PGM DATA
V
IH
V
IH
+5V
Programming Verification
W77IE58
Publication Release Date: October 20, 2005
- 71 - Revision A5
11. SECURITY BITS
During the on-chip ROM operation mode, the Flash EPROM can be programmed and verified
repeatedly. Until the code inside the ROM is confirmed OK, the code can be protected. The protection
of ROM and those operations on it are described below.
The W77IE58 has several Special Setting Registers, including the Security Register, which can not be
accessed in normal mode. These registers can only be accessed from the ROM operation mode.
Those bits of the Security Registers can not be changed once they have been programmed from high
to low. They can only be reset through erase-all operation. The Security Register is addressed in the
ROM operation mode by address #0FFFFh.
B0: Lock bit
This bit is used to protect the customer's program code in the W77IE58. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
ROM data and Special Setting Registers can not be accessed again.
B1: MOVC Inhibit
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set to
logic 0, a MOVC instruction in external program memory space will be able to access code only in the
external memory, not in the internal memory. A MOVC instruction in internal program memory space
will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,
there are no restrictions on the MOVC instruction.
W77IE58
- 72 -
12. ELECTRICAL CHARACTERISTICS
12.1 Absolute Maximum Ratings
PARAMETER SYMBOL CONDITION RATING UNIT
DC Power Supply VDDVSS -0.3 +7.0 V
Input Voltage VIN VSS -0.3 VDD +0.3 V
Operating Temperature TA -40 +85
°C
Storage Temperatute Tst -55 +150
°C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
12.2 D.C. Characteristics
(Fosc = 20 MHz, unless otherwise specified.)
SPECIFICATION
PARAMETER SYM.
MIN. MAX. UNIT
TEST CONDITIONS
Operating Voltage VDD 2.7 5.5 V
- 50 mA No load, VDD = RST = 5.5V
Operating Current IDD
15 mA No load, V
DD = RST = 3.0V
- 20 mA No load, VDD = 5.5V
Idle Current IIDLE
12 mA No load, V
DD = 3.0V
- 10
μA
No load, VDD = 5.5V
Power Down Current IPWDN
- 10
μA
No load, VDD = 3.0V
Input Current
P1, P2, P3, P4
I
IN1 -70 +10
μA
V
DD = 5.5V
VIN = 0V or VDD
Input Current RST
[*1]
IIN2 -10 +300
μA
V
DD = 5.5V
0<V
IN<VDD
Input Leakage Current
P0,
EA
I
LK -10 +10
μA
V
DD = 5.5V
0V<V
IN<VDD
Logic 1 to 0 Transition
Current P1, P2, P3, P4
I
TL
[*4]
-500 -200
μA
V
DD = 5.5V
VIN = 2.0V
Input Low Voltage 0 0.8 V VDD = 4.5V
P0, P1, P2, P3, ,P4,
EA
V
IL1
0 0.6 V V
DD = 3.0V
Input Low Voltage 0 0.8 V VDD = 4.5V
RST
[*1]
V
IL2
0 0.6 V V
DD = 3.0V
Input Low Voltage 0 0.8 V VDD = 4.5V
XTAL1
[*3]
V
IL3
0 0.4 V V
DD = 3.0V
Input High Voltage 2.4 VDD +0.2 V VDD = 5.5V
P0, P1, P2,
P3, P4, E
A
V
IH1
2.0 V
DD +0.2 V VDD = 3.0V

W77I058A25PL

Mfr. #:
Manufacturer:
Description:
IC MCU 8BIT 32KB FLASH 44PLCC
Lifecycle:
New from this manufacturer.
Delivery:
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