Connecting to the SPI bus M95160-x, M95080-x
10/49 Doc ID 8028 Rev 11
3 Connecting to the SPI bus
These devices are fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S
) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such
as the Read from Memory Array and Read Status Register instructions) have been clocked
into the device.
Figure 4. shows three devices, connected to an MCU, on an SPI bus. Only one device is
selected at a time, so only one device drives the Serial Data output (Q) line at a time, all the
others being high impedance.
Figure 4. Bus master and memory devices on the SPI bus
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Figure 4 shows an example of three memory devices connected to an MCU, on an SPI bus.
Only one memory device is selected at a time, so only one memory device drives the Serial
Data output (Q) line at a time, the other memory devices are high impedance.
The pull-up resistor R (represented in Figure 4) ensures that a device is not selected if the
Bus Master leaves the S
line in the high impedance state.
In applications where the Bus Master may be in a state where all input/output SPI buses are
high impedance at the same time (for example, if the Bus Master is reset during the
transmission of an instruction), the clock line (C) must be connected to an external pull-
down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low
(while the S
line is pulled high): this ensures that S and C do not become high at the same
time, and so, that the t
SHCH
requirement is met. The typical value of R is 100 kΩ.
AI12836b
SPI Bus Master
SPI Memory
Device
SDO
SDI
SCK
CQD
S
SPI Memory
Device
CQD
S
SPI Memory
Device
CQD
S
CS3 CS2 CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
W
HOLD
W
HOLD
W
HOLD
RR R
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
R
M95160-x, M95080-x Connecting to the SPI bus
Doc ID 8028 Rev 11 11/49
3.1 SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 5., is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 5. SPI modes supported
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
Operating features M95160-x, M95080-x
12/49 Doc ID 8028 Rev 11
4 Operating features
4.1 Supply voltage (V
CC
)
4.1.1 Operating supply voltage V
CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V
CC
voltage
within the specified [V
CC
(min), V
CC
(max)] range must be applied (see Ta ble 9, Ta bl e 10 and
Tabl e 1 1 ). This voltage must remain stable and valid until the end of the transmission of the
instruction and, for a Write instruction, until the completion of the internal write cycle (t
W
). In
order to secure a stable DC supply voltage, it is recommended to decouple the V
CC
line with
a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the V
CC
/V
SS
package
pins.
4.1.2 Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until V
CC
reaches the POR threshold voltage (this threshold is defined in DC characteristics tables 15,
16, 17, 18, 19 and 20 as V
RES
).
When V
CC
passes over the POR threshold, the device is reset and is in the following state:
in Standby Power mode
deselected (note that, to be executed, an instruction must be preceded by a falling
edge on Chip Select (S
))
Status Register value:
the Write Enable Latch (WEL) is reset to 0
Write In Progress (WIP) is reset to 0
The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits)
When V
CC
passes over the POR threshold, the device is reset and enters the Standby
Power mode. The device must not be accessed until V
CC
reaches a valid and stable V
CC
voltage within the specified [V
CC
(min), V
CC
(max)] range defined in Ta ble 9, Ta bl e 10 and
Tabl e 1 1 .
4.1.3 Power-up conditions
When the power supply is turned on, V
CC
rises continuously from V
SS
to V
CC
. During this
time, the Chip Select (S
) line is not allowed to float but should follow the V
CC
voltage. It is
therefore recommended to connect the S
line to V
CC
via a suitable pull-up resistor (see
Figure 4).
In addition, the Chip Select (S
) input offers a built-in safety feature, as the S input is edge
sensitive as well as level sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S
). This ensures that Chip Select
(S
) must have been high, prior to going low to start the first operation.
The V
CC
voltage has to rise continuously from 0 V up to the minimum V
CC
operating voltage
defined in Tabl e 9 , Table 1 0 and Ta ble 1 1 and the rise time must not vary faster than 1 V/µs.

M95080-RMB6TG

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
EEPROM 16 Kbit and 8 Kbit
Lifecycle:
New from this manufacturer.
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