OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

M95080-RMB6TG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P49
M95160-x, M95080-x Operating features
Doc ID 8028 Rev 11 13/49
4.1.4 Power-down
During power-down (continuous decrease in the V
CC
supply voltage below the minimum
V
CC
operating voltage defined in Ta ble 9 , Ta ble 1 0 and Table 1 1), the device must be:
● deselected (Chip Select S should be allowed to follow the voltage applied on V
CC
)
● in Standby Power mode (there should not be any internal write cycle in progress).
4.2 Active Power and Standby Power modes
When Chip Select (S) is low, the device is selected, and in the Active Power mode. The
device consumes I
CC
, as specified in Table 14. to Table 19.
When Chip Select (S
) is high, the device is deselected. If a Write cycle is not currently in
progress, the device then goes into the Standby Power mode, and the device consumption
drops to I
CC1
.
4.3 Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be selected, with Chip Select (S
) low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition, has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.
The Hold condition starts when the Hold (HOLD
) signal is driven low at the same time as
Serial Clock (C) already being low.
The Hold condition ends when the Hold (HOLD
) signal is driven high at the same time as
Serial Clock (C) already being low.
4.4 Status Register
Figure 6. shows the position of the Status Register in the control logic of the device. The
Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits
Operating features M95160-x, M95080-x
14/49 Doc ID 8028 Rev 11
4.5 Data protection and protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and
within applications that could experience problems if memory bytes are corrupted.
Consequently, the device features the following data protection mechanisms:
● Write and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
● All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–Power-up
– Write Disable (WRDI) instruction completion
– Write Status Register (WRSR) instruction completion
– Write (WRITE) instruction completion
● The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be
configured as read-only.
● The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits of the Status
Register to be protected.
For any instruction to be accepted, and executed, Chip Select (S
) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points need to be noted in the previous sentence:
● The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
● The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus
transaction for some other device on the SPI bus.
Table 3. Write-protected block size
Status Register bits
Protected block
Protected array addresses
BP1 BP0 M95160-x M95080-x
0 0 none none none
0 1 Upper quarter 0600h - 07FFh 0300h - 03FFh
1 0 Upper half 0400h - 07FFh 0200h - 03FFh
1 1 Whole memory 0000h - 07FFh 0000h - 03FFh
M95160-x, M95080-x Memory organization
Doc ID 8028 Rev 11 15/49
5 Memory organization
The memory is organized as shown in Figure 6.
Figure 6. Block diagram
AI01272d
HOLD
S
W
Control logic
High voltage
generator
I/O shift register
Address register
and counter
Data
register
1 page
X decoder
Y decoder
C
D
Q
Size of the
read-only
EEPROM
area
Status
Register
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P49

M95080-RMB6TG

Mfr. #:
Buy M95080-RMB6TG
Manufacturer:
STMicroelectronics
Description:
EEPROM 16 Kbit and 8 Kbit
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet