M95160-x, M95080-x DC and AC parameters
Doc ID 8028 Rev 11 35/49
Table 24. AC characteristics (M95160-W and M95080-W, device grade 6)
Test conditions specified in Table 13. and Table 10.
Symbol Alt. Parameter Min. Max. Unit
f
C
f
SCK
Clock frequency D.C. 10 MHz
t
SLCH
t
CSS1
S active setup time 30 ns
t
SHCH
t
CSS2
S not active setup time 30 ns
t
SHSL
t
CS
S deselect time 40 ns
t
CHSH
t
CSH
S active hold time 30 ns
t
CHSL
S not active hold time 30 ns
t
CH
(1)
1. t
CH
+ t
CL
must never be lower than the shortest possible clock period, 1/f
C
(max).
t
CLH
Clock high time 40 ns
t
CL
(1)
t
CLL
Clock low time 40 ns
t
CLCH
(2)
2. Value guaranteed by characterization, not 100% tested in production.
t
RC
Clock rise time 2 µs
t
CHCL
(2)
t
FC
Clock fall time 2 µs
t
DVCH
t
DSU
Data in setup time 10 ns
t
CHDX
t
DH
Data in hold time 10 ns
t
HHCH
Clock low hold time after HOLD not active 30 ns
t
HLCH
Clock low hold time after HOLD active 30 ns
t
CLHL
Clock low set-up time before HOLD active 0 ns
t
CLHH
Clock low set-up time before HOLD not
active
0ns
t
SHQZ
(2)
t
DIS
Output disable time 40 ns
t
CLQV
t
V
Clock low to output valid 40
(3)
3. t
CLQV
must be compatible with t
CL
(clock low time): if the SPI bus master offers a Read setup time t
SU
=
0ns, t
CL
can be equal to (or greater than) t
CLQV
. In all other cases, t
CL
must be equal to (or greater than)
t
CLQV
+ t
SU
.
ns
t
CLQX
t
HO
Output hold time 0 ns
t
QLQH
(2)
t
RO
Output rise time 40 ns
t
QHQL
(2)
t
FO
Output fall time 40 ns
t
HHQV
t
LZ
HOLD high to output valid 40 ns
t
HLQZ
(2)
t
HZ
HOLD low to output high-Z 40 ns
t
W
t
WC
Write time 5 ms
