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M95080-RMB6TG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P49
Instructions M95160-x, M95080-x
16/49 Doc ID 8028 Rev 11
6 Instructions
Each instruction starts with a single-byte code, as summarized in Table 4.
If an invalid instruction is sent (one not contained in Table 4.), the device automatically
deselects itself.
6.1 Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 7., to send this instruction to the device, Chip Select (S
) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected, by Chip Select (S
) being driven
high.
Figure 7. Write Enable (WREN) sequence
Table 4. Instruction set
Instruction Description Instruction format
WREN Write Enable 0000 0110
WRDI Write Disable 0000 0100
RDSR Read Status Register 0000 0101
WRSR Write Status Register 0000 0001
READ Read from Memory Array 0000 0011
WRITE Write to Memory Array 0000 0010
C
D
AI02281E
S
Q
21 34567
High Impedance
0
Instruction
M95160-x, M95080-x Instructions
Doc ID 8028 Rev 11 17/49
6.2 Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 8., to send this instruction to the device, Chip Select (S
) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S
) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
● Power-up
● WRDI instruction execution
● WRSR instruction completion
● WRITE instruction completion.
Figure 8. Write Disable (WRDI) sequence
C
D
AI03750D
S
Q
21 34567
High Impedance
0
Instruction
Instructions M95160-x, M95080-x
18/49 Doc ID 8028 Rev 11
6.3 Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 9.
The status and control bits of the Status Register are as follows:
6.3.1 WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
6.3.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.
6.3.3 BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in Table 5.) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
6.3.4 SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W
) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Protect (W
) is driven low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 5. Status Register format
b7 b0
SRWD 0 0 0 BP1 BP0 WEL WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P49

M95080-RMB6TG

Mfr. #:
Buy M95080-RMB6TG
Manufacturer:
STMicroelectronics
Description:
EEPROM 16 Kbit and 8 Kbit
Lifecycle:
New from this manufacturer.
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