72T6360L6BB Datasheet 72T6360L6BB, 72T6360L6BBG, 72T6360L7-5BB | P1-P3

FEBRUARY 2009

2.5V SEQUENTIAL FLOW-CONTROL DEVICE

36 BIT WIDE CONFIGURATION

For use with 128Mb to 256Mb DDR SDRAM

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT72T6360

FEATURES

• Product to be used with single or multiple external DDR SDRAM

to provide significant storage capability of up to 1Gb density

• 166MHz operation (6ns read/write cycle time)

• User selectable input and output port bus-sizing

- x36in to x36out

- x36in to x18out

- x36in to x9out

- x18in to x36out

- x18in to x18out

- x18in to x9out

- x9in to x36out

- x9in to x18out

- x9in to x9out

• For other bus configurations see IDT72T6480 (x12, x24, or x48)

• 2.5V-LVTTL or 3.3V-LVTTL configured ports

• Independent and simultaneous read and write access

• User selectable synchronous/asynchronous read and write

port timing

• IDT Standard mode or FWFT mode of operation

• Empty and full flags for monitoring memory status

• Programmable Almost-Empty and Almost-Full flags, each flag

can default to one of four preselected offsets or serially

programmed to a specific value

• Selectable synchronous/asynchronous timing modes for

Almost-Empty and Almost-Full flags

• Master Reset clears all data and settings

••

• Partial Reset clears data, but retains programmable settings

••

• Depth expandable with multiple devices for densities greater

than 1Gb

••

• Width expandable with multiple devices for bus widths greater

than 36 bits

••

• JTAG functionality (Boundary Scan)

••

• Available in a 324-pin PBGA, 1mm pitch, 19mm x 19mm

••

• HIGH performance 0.18

µµ

µm CMOS technology

••

• Industrial temperature range (-40

°°

°C to +85

°°

°C) is available

••

• Supports industry standard DDR specifications, including

Samsung, Micron, and Infineon memories

FUNCTIONAL BLOCK DIAGRAM

36-bits 36-bits 36-bits

6357 drw01

x36, x18, or x9

High Density DDR SDRAM

x16, x32, x36, or x64

128Mb to 256Mb

DDR SDRAM

Control Logic

x36, x18, or x9

IDT72T6360

Sequential Flow Control Device

Data

Addr

WE CAS RAS

Flag

Logic

JTAG

Control

(Boundary Scan)

FWFT

FSEL[1:0]

FF/IR

PAF

PAE

Write

Control Logic

Read

Control Logic

Reset

Logic

MRS

PRS

I/O Bus

Configuration

IOSEL

BM[3:0]

WEN

WCLK/WR

REN

RCLK/RD

RCS

Input Register

EF/OR

Output Register

WCS

ASYW

MCLK

ASYR

DQS

TCK/SCLK

TMS

TDO/SO

TDI/SI

IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE

x9, x18, x36 BIT WIDE CONFIGURATION

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

FEBRUARY 10, 2009

Table of Contents

Features ......................................................................................................................................................................................................................... 1

Description ...................................................................................................................................................................................................................... 4

Pin Configuration ............................................................................................................................................................................................................. 6

Pin Descriptions ..........................................................................................................................................................................................................7-10

-Read Port Interface ............................................................................................................................................................................... 7

-Write Port Interface ................................................................................................................................................................................ 7

-Memory Interface.................................................................................................................................................................................. 8

-Control and Feature Interface ............................................................................................................................................................... 8

-Power and Ground Signals................................................................................................................................................................. 10

Detailed Descriptions ..................................................................................................................................................................................................... 11

Functional Descriptions .................................................................................................................................................................................................. 22

Signal Descriptions ........................................................................................................................................................................................................ 23

Device Characteristics ................................................................................................................................................................................................... 27

AC Test Conditions ........................................................................................................................................................................................................ 29

AC Electrical Characteristics ........................................................................................................................................................................................... 30

JTAG Timing Specifications ............................................................................................................................................................................................ 45

Depth Expansion Configuration ..................................................................................................................................................................................... 49

Width Expansion Configuration ...................................................................................................................................................................................... 50

List of Tables

Table 1 – DDR SDRAM Minimum Specifications ............................................................................................................................................................. 11

Table 2 – Supported Memory Vendors .......................................................................................................................................................................... 11

Table 3 – Total Possible External Memory Configurations............................................................................................................................................... 12

Table 4 – SFC to DDR SDRAM interface connections .................................................................................................................................................... 14

Table 5 – Total useable memory based on various configurations................................................................................................................................... 18

Table 6 – IDT72T6360 Maximum Frequency Based on 166MHz DDR SDRAM ............................................................................................................ 19

Table 7 – IDT72T6360 Maximum Frequency Based on 133MHz DDR SDRAM ............................................................................................................ 19

Table 8 – MIC[2:0] Configurations.................................................................................................................................................................................. 20

Table 9 – Memory Configurations Settings ..................................................................................................................................................................... 21

Table 10 – Device configuration ..................................................................................................................................................................................... 22

Table 12– Number of Bits Required for Offset Registers .................................................................................................................................................. 22

Table 11– Default Programmable Flag Offsets ................................................................................................................................................................. 22

Table 13 – Bus-Matchings ............................................................................................................................................................................................. 24

Table 14 – MTYPE[1:0] Configurations .......................................................................................................................................................................... 25

Table 15 – Parameters affected by I/O selection ............................................................................................................................................................. 25

IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE

x9, x18, x36 BIT WIDE CONFIGURATION

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

FEBRUARY 10, 2009

List of Figures

Figure 1. Sequential Flow-Control Device Block Diagram ............................................................................................................................................... 5

Figure 2a. Configuration 1 - Two Chip Solution .............................................................................................................................................................. 13

Figure 2b. Configuration 2 - Two Chip Solution .............................................................................................................................................................. 13

Figure 2c. Configuration 3 - Three Chip Solution ........................................................................................................................................................... 13

Figure 2d. Configuration 4 - Three Chip Solution ........................................................................................................................................................... 13

Figure 2e. Configuration 5 - Three Chip Solution ........................................................................................................................................................... 13

Figure 2f. Configuration 6 - Four Chip Solution .............................................................................................................................................................. 13

Figure 2g. Configuration 7 - Five Chip Solution.............................................................................................................................................................. 13

Figure 3. Memory Interface Connection (Single Chip) ................................................................................................................................................... 17

Figure 4. Memory Interface Connection (Two Chip) ...................................................................................................................................................... 17

Figure 5a. AC Test Load................................................................................................................................................................................................ 29

Figure 5b. Lumped Capacitive Load, Typical Derating ................................................................................................................................................... 29

Figure 6. Master Reset and Initialization ......................................................................................................................................................................... 32

Figure 7. Partial Reset ................................................................................................................................................................................................... 33

Figure 8. Write First Word Cycles - IDT Standard Mode................................................................................................................................................. 34

Figure 9. Write First Word Cycles - FWFT Mode............................................................................................................................................................ 34

Figure 10. Empty Boundary - IDT Standard Mode ........................................................................................................................................................ 35

Figure 11. Empty Boundary - FWFT Mode.................................................................................................................................................................... 35

Figure 12. Full Boundary - IDT Standard Mode ............................................................................................................................................................ 36

Figure 13. Full Boundary - FWFT Mode ....................................................................................................................................................................... 36

Figure 14. Output Enable............................................................................................................................................................................................... 37

Figure 15. Read Chip Select ......................................................................................................................................................................................... 37

Figure 16. Write Chip Select .......................................................................................................................................................................................... 37

Figure 17. Bus-Matching Configuration - x36 In to x18 Out - IDT Standard Mode .......................................................................................................... 38

Figure 18. Bus-Matching Configuration - x36 In to x9 Out - IDT Standard Mode ............................................................................................................ 38

Figure 19. Bus-Matching Configuration - x18 In to x36 Out - IDT Standard Mode .......................................................................................................... 39

Figure 20. Bus-Matching Configuration - x9 In to x36 Out - IDT Standard Mode ............................................................................................................ 39

Figure 21. Synchronous PAE Flag - IDT Standard Mode and FWFT Mode ................................................................................................................... 40

Figure 22. Synchronous PAF Flag - IDT Standard Mode and FWFT Mode ................................................................................................................... 40

Figure 23. Asynchronous Read and PAF Flag - IDT Standard Mode............................................................................................................................. 41

Figure 24. Asynchronous Write and PAE Flag - IDT Standard Mode.............................................................................................................................. 41

Figure 25. Asynchronous Write and PAF Flag - IDT Standard Mode.............................................................................................................................. 41

Figure 26. Asynchronous Empty Boundary - IDT Standard Mode.................................................................................................................................. 42

Figure 27. Asynchronous Full Boundary - IDT Standard Mode...................................................................................................................................... 42

Figure 28. Asynchronous Read and PAE Flag - IDT Standard Mode............................................................................................................................. 42

Figure 29. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) ...................................................................................... 43

Figure 30. Reading of Programmable Flag Registers (IDT Standard and FWFT Modes) ............................................................................................... 43

Figure 31. Standard JTAG Timing.................................................................................................................................................................................. 44

Figure 32. JTAG Architecture ......................................................................................................................................................................................... 45

Figure 33. TAP Controller State Diagram ....................................................................................................................................................................... 46

Figure 34. Depth Expansion Configuration in IDT Standard Mode ................................................................................................................................. 49

Figure 35. Depth Expansion Configuration in FWFT Mode ............................................................................................................................................ 49

Figure 36. Width Expansion Configuration in IDT Standard Mode and FWFT Mode ....................................................................................................... 50

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72T6360L6BB

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IC SEQUENTIAL FLOW-CTRL 324PBGA

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72T6360L6BB

72T6360L6BB

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