13
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009
CONNECTING THE DDR SDRAM
Below are the various chipset solution configurations available to the
sequential flow-control device (see Figure 2a-2g). The external memory
interface is designed to seamlessly connect one or more DDR SDRAMs. The
output signal names should be connected directly to its corresponding input
signal on the DDR SDRAM. There are three signals on the DDR SDRAM that
must be tied to a static state. CKE, CS, and DM. Table 4 outlines how to connect
the many interface pins to the DDR SDRAM(s). Figure 3 and 4 are some
examples of the memory interface connections for various density configura-
tions. For information on DDR SDRAM layout recommendations, please see
IDT application note AN-423.
Figure 2b
(1)
. Configuration 2 - Two Chip Solution
Figure 2c. Configuration 3 - Three Chip Solution
Figure 2e
(1)
. Configuration 5 - Three Chip Solution
Figure 2f
(1)
. Configuration 6 - Four Chip Solution
Figure 2g
(1)
. Configuration 7 - Five Chip Solution
Figure 2a. Configuration 1 - Two Chip Solution
IDT
SFC
128Mb or
256Mb
DDR
SDRAM
6357 drw04
Data Bus
32
12
Address Bus
IDT
SFC
256Mb
DDR
SDRAM
6357 drw05
Data Bus
16
13
Address Bus
64
32
IDT
SFC
128Mb or
256Mb
DDR
SDRAM
6357 drw06
Data Bus
12
32
12
Address Bus
32
16
IDT
SFC
256Mb
DDR
SDRAM
6357 drw08
Data Bus
13
16
13
Address Bus
4
36
13
IDT
SFC
256Mb
DDR
SDRAM
6357 drw09
Data Bus
13
16
13
Address Bus
16
64
16
16
IDT
SFC
256Mb
DDR
SDRAM
13
6357 drw10
Data Bus
13
Address Bus
Figure 2d. Configuration 4 - Three Chip Solution
36
4
IDT
SFC
128Mb or
256Mb
DDR
SDRAM
6357 drw07
Data Bus
12
32
12
Address Bus
DDR SDRAM: 256Mb [16Mb x 16]
Total Memory Density: 256Mb
Useable Memory
(2)
: 216Mb
DDR SDRAM: 128Mb [4Mb x 32] or 256Mb [8Mb x 32]
Total Memory Density: 256Mb or 512Mb
Useable Memory
(2)
: 216Mb or 504Mb
DDR SDRAM: 256Mb [16Mb x 16]
Total Memory Density: 512Mb
Useable Memory
(2)
: 504Mb
DDR SDRAM: 256Mb [16Mb x 16]
Total Memory Density: 768Mb
Useable Memory
(2)
: 567Mb
DDR SDRAM: 256Mb [16Mb x 16]
Total Memory Density: 1Gb
Useable Memory
(2)
: 1008Mb
DDR SDRAM: 128Mb [4Mb x 32] or 256Mb [8Mb x 32]
Total Memory Density: 128Mb or 256Mb
Useable Memory
(2)
: 108Mb or 252Mb
NOTES:
1. 12-bit address bus for 8Mb x16
13-bit address bus for 16Mb x16
2. Refer to Total Available Memory Usage section for details.
DDR SDRAM: 128Mb [4Mb x 32] or 256Mb [8Mb x 32]
Total Memory Density: 256Mb or 512Mb
Useable Memory
(2)
: 108Mb or 252Mb
14
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009
TABLE 4 – SFC TO DDR SDRAM INTERFACE CONNECTIONS
SFC Outputs DDR SDRAM
DQ[31:0] DQ[31:0]
DQS[3:0] DQS[3:0]
A[11:0] A[11:0]
CK, CK CK, CK
RAS, CAS RAS, CAS
BA[1:0] BA[1:0]
WE WE
DDR SDRAM Hard wired pins
CKE VCC
CS GND
DM[3:0] GND
SFC Hard wired pins
DQ[63:32] VCC
DQS[7:4] VCC
A12 VCC
CONFIGURATION 1
SFC Outputs DDR SDRAM
DQ[15:0] DQ[15:0]
DQS0 LDQS
DQS1 UDQS
A[12:0] A[12:0]
CK, CK CK, CK
RAS, CAS RAS, CAS
BA[1:0] BA[1:0]
WE WE
DDR SDRAM Hard wired pins
CKE VCC
CS GND
LDM GND
UDM GND
SFC Hard wired pins
DQ[63:16] VCC
DQS[7:2] VCC
CONFIGURATION 2
IDT
SFC
128Mb or
256Mb
DDR
SDRAM
6357 drw04
Data Bus
32
12
Address Bus
IDT
SFC
256Mb
DDR
SDRAM
6357 drw05
Data Bus
16
13
Address Bus
SFC Outputs DDR SDRAM #1 DDR SDRAM #2
DQ[31:0] DQ[31:0] --
DQ[35:32] -- DQ[3:0]
DQ[63:36] -- --
DQS[3:0] DQS[3:0] --
DQS[7:4] -- DQS[3:0]
A[11:0] A[11:0] A[11:0]
CK, CK CK, CK CK, CK
RAS, CAS RAS, CAS RAS, CAS
BA[1:0] BA[1:0] BA[1:0]
WE WE WE
DDR SDRAM Hard wired pins
CKE VCC
CS GND
DM[3:0] GND
DQ[31:4] VCC
SFC Hard wired pins
A12 VCC
CONFIGURATION 4
36
4
IDT
SFC
128Mb or
256Mb
DDR
SDRAM
6357 drw07
Data Bus
12
32
12
Address Bus
SFC Outputs DDR SDRAM #1 DDR SDRAM #2
DQ[31:0] DQ[31:0] --
DQ[63:32] -- DQ[31:0]
DQS[3:0] DQS[3:0] --
DQS[7:4] -- DQS[3:0]
A[11:0] A[11:0] A[11:0]
CK, CK CK, CK CK, CK
RAS, CAS RAS, CAS RAS, CAS
BA[1:0] BA[1:0] BA[1:0]
WE WE WE
DDR SDRAM Hard wired pins
CKE VCC
CS GND
DM[3:0] GND
SFC Hard wired pins
A12 VCC
CONFIGURATION 3
64
32
IDT
SFC
128Mb or
256Mb
DDR
SDRAM
6357 drw06
Data Bus
12
32
12
Address Bus
15
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009
TABLE 4 – SFC TO DDR SDRAM INTERFACE CONNECTIONS(Continued)
SFC Outputs DDR SDRAM #1 DDR SDRAM #2
DQ[15:0] DQ[15:0] --
DQ[31:16] -- DQ[15:0]
DQS0 LDQS --
DQS1 UDQS --
DQS2 -- LDQS
DQS3 -- UDQS
A[12:0] A[12:0] A[12:0]
CK, CK CK, CK CK, CK
RAS, CAS RAS, CAS RAS, CAS
BA[1:0] BA[1:0] BA[1:0]
WE WE WE
DDR SDRAM Hard wired pins
CKE VCC
CS GND
LDM GND
UDM GND
SFC Hard wired pins
DQ[63:32] VCC
DQS[7:2] VCC
CONFIGURATION 5
SFC Outputs DDR SDRAM #1 DDR SDRAM #2 DDR SDRAM #3
DQ[15:0] DQ[15:0] -- --
DQ[31:16] -- DQ[15:0] --
DQ[35:32] -- -- DQ[3:0]
DQS0 LDQS -- --
DQS1 UDQS -- --
DQS2 -- LDQS --
DQS3 -- UDQS --
DQS4 -- -- LDQS
DQS5 -- -- UDQS
A[12:0] A[12:0] A[12:0] A[12:0]
CK, CK CK, CK CK, CK CK, CK
RAS, CAS RAS, CAS RAS, CAS RAS, CAS
BA[1:0] BA[1:0] BA[1:0] BA[1:0]
WE WE WE WE
DDR SDRAM Hard wired pins
CKE VCC
CS GND
LDM GND
UDM GND
DQ[15:4] VCC
SFC Hard wired pins
DQ[63:36] VCC
DQS[7:6] VCC
CONFIGURATION 6
32
16
IDT
SFC
256Mb
DDR
SDRAM
6357 drw08
Data Bus
13
16
13
Address Bus
4
36
13
IDT
SFC
256Mb
DDR
SDRAM
6357 drw09
Data Bus
13
16
13
Address Bus
16

72T6360L6BB

Mfr. #:
Manufacturer:
Description:
IC SEQUENTIAL FLOW-CTRL 324PBGA
Lifecycle:
New from this manufacturer.
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