49
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009
GND
Transfer Clock
FWFT FWFT
WCLK
WEN
FF
Dn
IDEM
SFC
#1
RCLK
OR
REN
Qn
WCLK
WEN
IR
Dn
IDEM
SFC
#2
RCLK
EF
REN
Qn
V
CC
V
CC
Write Clock
Write Enable
Full Flag
Data Inputs
Read Clock
Empty Flag
Read Enable
Data Outputs
6357 drw48
V
CC
V
CC
Transfer Clock
FWFT FWFT
WCLK
WEN
IR
Dn
IDEM
SFC
#1
RCLK
OR
REN
Qn
WCLK
WEN
IR
Dn
IDEM
SFC
#2
RCLK
OR
REN
Qn
GND
GND
Write Clock
Write Enable
Input Ready Flag
Data Inputs
Read Clock
Output Ready Flag
Read Enable
Data Outputs
6357 drw49
Figure 34. Depth Expansion Configuration in IDT Standard Mode
Figure 35. Depth Expansion Configuration in FWFT Mode
DEPTH EXPANSION CONFIGURATION
The sequential flow-control (SFC) device can be connected with multiple
SFCs in depth expansion to provide additional storage density that’s greater
than 1Gb. In depth expansion mode, two or mode devices are connected
through a common transfer interface, as shown in Figure 34. The transfer clock
can be a separate free-running clock or driven from the same system write or
read clock.
In depth expansion configuration, the first word written to an empty configu-
ration will pass from the first SFC to the next until it appears on the second (or
last) SFC in the chain. If no reads are performed, data will begin accumulating
in the second SFC until it is full. Once the second SFC is full it will disable the
REN to the first SFC. At this point data will begin accumulating in the first SFC.
Once both devices are full, the entire configuration is full and the full flag indicator
will go LOW.
For an empty configuration, the amount of time it takes for the empty flag of
the second (or last) SFC in the chain to go LOW (i.e. valid data available to be
read out of the device) after a word has been written into the first FIFO is the
sum of the delays for each individual SFC:
(N - 1) x (4 x transfer clock) + 3 x RCLK
Where N is the number of SFCs in the chain and RCLK is the RCLK period
in ns. This latency is only noticeable for the first word written to an empty
configuration. There will be no delay evident for subsequent words written into
the chain.
In the full configuration, the amount of time it takes for the FF of the first SFC
to go from LOW to HIGH after reading one word from the chain is the sum of the
delays for each individual SFC:
(N - 1) x (3 x transfer clock) + 2 x WCLK
Depth expansion is available in both IDT Standard mode and First Word Fall
Through (FWFT) mode. If IDT Standard mode is selected, the IDEM signal
needs to be HIGH. If FWFT mode is selected, the IDEM signal needs to be LOW.
50
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009
WIDTH EXPANSION CONFIGURATION
The sequential flow-control (SFC) device can be connected with another
SFCs in width expansion to support bus-widths greater than 36-bits. This
configuration connects the input and output bus of two devices together to create
a wider bus. The read and write clocks for each device are driven with a clock
driver. The empty and full flags of both devices are connected to a logic gate
(AND/OR) depending on whether IDT Standard mode or FWFT mode is
selected. Because of the variation in skew between the read clock and write
clock, it is possible for EF/FF deassertion and IR/OR assertion to vary from one
cycle between the devices. The logic gate connected to the status flags will create
a composite flag that will update the status of both SFC devices to represent a
more accurate status of the configuration. To minimize the skew between the
two write and read clocks, a clock driver (IDT5T905 recommended) is used
to drive the input clocks for both SFC devices. Figure 36 illustrates the width
expansion configuration.
WCLK
WEN
Dn
RCLK
REN
EF
/
OR
Qn
SFC
FF
/
IR
Write Clock
Write Enable
Full Flag/Input Ready
Data Inputs
Read Clock
Empty Flag/Output Ready
Read Enable
Data Outputs
64
36
36
WCLK
WEN
Dn
RCLK
REN
EF/OR
Qn
SFC
FF/IR
Gate
(1)
Full Flag/Input Ready
Gate
(1)
Empty Flag/Output Ready
64
Clock Driver
IDT5T905
Clock Driver
IDT5T905
Write Clock Read Clock
Clock Driver
IDT5T905
Clock Driver
IDT5T905
36
36
6357 drw50
Figure 36. Width Expansion Configuration in IDT Standard Mode and FWFT Mode
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output signals directly together.
51
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1533
San Jose, CA 95138 fax: 408-284-2775 email: Flow-Controlhelp@idt.com
www.idt.com
ORDERING INFORMATION
Plastic Ball Grid Array (PBGA, BB324)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Low Power
6357 drwlast
Commercial Only
Commercial and Industrial
L
XXXXX
Device Type
X
Power
XX
Speed
X
Package
X
Process /
Temperature
Range
BLANK
I
(1)
72T6360 2.5V Sequential Flow Control Device configurable to x9, x18, or x36
Clock Cycle Time (t
CLK
)
Speed in Nanoseconds
BB
6
7-5
DATASHEET DOCUMENT HISTORY
07/29/2004 pgs. 1, 4, 7-11, 13-25, 27-43, 47, 49, and 51.
04/11/2005 pgs. 6 and 10.
06/28/2005 pg. 16.
10/10/2005 pgs. 1, 15, and 16.
02/10/2009 pg. 51.

72T6360L6BB

Mfr. #:
Manufacturer:
Description:
IC SEQUENTIAL FLOW-CTRL 324PBGA
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet