47
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009
THE INSTRUCTION REGISTER
The instruction register (IR) is eight bits long and tells the device what
instruction is to be executed. Information contained in the instruction includes the
mode of operation (either normal mode, in which the device performs its normal
logic function, or test mode, in which the normal logic function is inhibited or
altered), the test operation to be performed, which of the four data registers is
to be selected for inclusion in the scan path during data-register scans, and the
source of data to be captured into the selected data register during Capture-DR.
TEST DATA REGISTER
The Test Data register contains three test data registers: the Bypass, the
Boundary Scan register and Device ID register.
These registers are connected in parallel between a common serial input
and a common serial data output.
The following sections provide a brief description of each element. For a
complete description, refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
TEST BYPASS REGISTER
The register is used to allow test data to flow through the device from TDI
to TDO. It contains a single stage shift register for a minimum length in the serial
path. When the bypass register is selected by an instruction, the shift register
stage is set to a logic zero on the rising edge of TCLK when the TAP controller
is in the Capture-DR state.
The operation of the bypass register should not have any effect on the
operation of the device in response to the BYPASS instruction.
THE BOUNDARY-SCAN REGISTER
The boundary-scan register (BSR) contains one boundary-scan cell
(BSC) for each normal-function input pin and one BSC for each normal-function
I/O pin (one single cell for both input data and output data). The BSR is used
1) to store test data that is to be applied externally to the device output pins, and/
or 2) to capture data that appears internally at the outputs of the normal on-chip
logic and/or externally at the device input pins.
THE DEVICE IDENTIFICATION REGISTER
The Device Identification Register is a Read Only 32-bit register used to
specify the manufacturer, part number and version of the device to be
determined through the TAP in response to the IDCODE instruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is
dropped in the 11-bit Manufacturer ID field.
For the IDT72T6360, the Part Number field contains the following values:
IDT72T6360 JTAG Device Identification Register
31(MSB) 28 27 12 11 1 0(LSB)
Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)
0000 0033 (hex) 1
JTAG INSTRUCTION REGISTER
The Instruction register allows an instruction to be serially input into the
device when the TAP controller is in the Shift-IR state. The instruction is decoded
to perform the following:
• Select test data registers that may operate while the instruction is
current. The other test data registers should not interfere with chip
operation and the selected data register.
• Define the serial test data register path that is used to shift data between
TDI and TDO during data register scanning.
The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode
16 different possible instructions. Instructions are decoded as follows.
Hex Instruction Function
Value
0000 EXTEST Test external pins
0001 SAMPLE/PRELOAD Select boundary scan register
0002 IDCODE Selects chip identification register
0003 HIGH-IMPEDANCE Puts all outputs in high-impedance state
0008 CLAMP Fix the output chains to scan chain values
000F BYPASS Select bypass register
Private Several combinations are private (for IDT
internal use). Do not use codes other than
those identified above.
JTAG INSTRUCTION REGISTER DECODING
The following sections provide a brief description of each instruction. For
a complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
EXTEST
The required EXTEST instruction places the device into an external
boundary-test mode and selects the boundary-scan register to be connected
between TDI and TDO. During this instruction, the boundary-scan register is
accessed to drive test data off-chip via the boundary outputs and receive test
data off-chip via the boundary inputs. As such, the EXTEST instruction is the
workhorse of IEEE. Std 1149.1, providing for probe-less testing of solder-joint
opens/shorts and of logic cluster function.
SAMPLE/PRELOAD
The required SAMPLE/PRELOAD instruction allows the device to remain in
a normal functional mode and selects the boundary-scan register to be
connected between TDI and TDO. During this instruction, the boundary-scan
register can be accessed via a data scan operation, to take a sample of the
functional data entering and leaving the device. This instruction is also used to
preload test data into the boundary-scan register before loading an EXTEST
instruction.
IDCODE
The optional IDCODE instruction allows the device to remain in its functional
mode and selects the optional device identification register to be connected
between TDI and TDO. The device identification register is a 32-bit shift register
containing information regarding the device manufacturer, device type, and
version code. Accessing the device identification register does not interfere with
the operation of the device. Also, access to the device identification register
should be immediately available, via a TAP data-scan operation, after power-
up of the device or by otherwise moving to the Test-Logic-Reset state.
Device Part# Field
IDT72T6360 0437 (hex)
