32
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009
Figure 6. Master Reset and Initialization
tRSF
IDT Standard Mode
Synchronous read port selected
Synchronous write port selected
If OE = HIGH
Asynchronous read port selected
Asynchronous write port selected
2.5V I/O voltage selected
MRS
REN
WEN
SREN
SWEN
EF
OR
FF
IR
CK
CK
Q[35:0]
FWFT
ASYR
ASYW
IOSEL
PAF
PAE
IDEM
Depth Expansion in IDT Standard Mode
Depth Expansion in FWFT Standard Mode
tRSU
tRSU
tRSU
tRSU
tRSF
tRSU
tRSF
If OE = LOW
tPL
tPL
tPL
tPL
tRSU
tRSU
tRSU
3.3V I/O voltage selected
The clock may not be locked to the required operating frequency before
tPL
The clock may not be locked to the required operating frequency before
tPL
tRS
tRSF
tRH
tRH
tRH
tRH
tRSU
6357 drw20
FWFT Mode
If FWFT mode is selected
If IDT mode is selected
If FWFT mode is selected
If IDT mode is selected
NOTE:
1. For other signals that are latched during master reset, refer to Master Reset and Device Configuration section.
Symbol Parameter Min. Max. Unit
tRS Reset Pulse Width 10 — ns
tRSU Reset Setup Time 15 — ns
tRSH Reset Hold Time 10 — ns
tPL Reset to PLL Lock 20 — µs
tRSF Reset to Flag and Output — 15 ns