18
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009
TOTAL AVAILABLE MEMORY USAGE
The sequential flow-control (SFC) is designed to efficiently use as much of
the DDR SDRAM memory as possible, but due to the discontinuity between the
SFC bus width (x36) and the DDR SDRAM interface (x16 or x32), some
columns in a row of the SDRAM will not be used. As a result, the total usable
memory will be slightly less than the total available memory in the SDRAM. Table
5 outlines the total usable memory for the various configurations depending on
whether or not the Error Detection and Correction (EDC) feature is selected.
If the EDC feature is selected, 8 syndrome bits will be generated per every 64
bits of data. Therefore every third write burst to the SDRAM will send out the
8 syndrome bits, resulting in 24 unused bits inthe column. Therefore, using the
EDC feature, there will be significantly less usable memory of data storage. The
EDC function is described in the Error Detection and Correction section of this
datasheet.
Total DDR SDRAM Total Usable Total Usable
Density Memory (EDC off) Memory (EDC on)
Configuration 1
1 x [4Mb x 32] 128Mb 108Mb 72Mb
1 x [8Mb x 32] 256Mb 252Mb 144Mb
Configuration 2
1 x [8Mb x 16] 128Mb 108Mb 72Mb
1 x [16Mb x 16] 256Mb 216Mb 144Mb
Configuration 3
2 x [4Mb x 32] 256Mb 216Mb 144Mb
2 x [8Mb x 32] 512Mb 504Mb 288Mb
Configuration 4
2 x [4Mb x 32] 256Mb 122Mb 108Mb
2 x [8Mb x 32] 512Mb 284Mb 252Mb
Configuration 5
2 x [8Mb x 16] 256Mb 252Mb 144Mb
2 x [16Mb x 16] 512Mb 504Mb 288Mb
Configuration 6
3 x [8Mb x 16] 384Mb 284Mb 252Mb
3 x [16Mb x 16] 768Mb 567Mb 504Mb
Configuration 7
4 x [8Mb x 16] 512Mb 504Mb 288Mb
4 x [16Mb x 16] 1Gb 1008Mb 576Mb
TABLE 5 – TOTAL USEABLE MEMORY BASED ON VARIOUS CONFIGURATIONS
